CY7C68320C-100AXC Cypress Semiconductor Corp, CY7C68320C-100AXC Datasheet - Page 9

• Manufacturer Part Number: CY7C68320C-100AXC
• Description: IC USB 2.0 BRIDGE AT2LP 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB AT2LP™r
• Type: USB to ATA Bridger

Specifications of CY7C68320C-100AXC

• Package / Case: 100-LQFP
• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Operating Supply Voltage: 3.3 V
• Supply Current: 50 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4615B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2267; CY7C68320C-100AXC

Pin Descriptions
The following table lists the pinouts for the 56-pin SSOP, 56-pin QFN, and 100-pin TQFP package options for the AT2LP. Refer to the
“Pin Diagrams”
on the CY7C68300A pinout, refer to the CY7C68300A data sheet that is found in the ’EZ-USB AT2’ folder of the CY4615C reference
design kit CD.
Table 1. AT2LP Pin Descriptions
Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode)
Document 001-05809 Rev. *B
Notes
1. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See
2. A ‘#’ sign after the pin name indicates that it is active LOW.
3. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320C/CY7C68321C.
TQFP
26
100
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
11
1
2
3
4
5
6
7
8
9
[3]
QFN
13
N/A
N/A
N/A
N/A
56
55
56
10
11
12
14
1
2
3
4
5
6
7
8
9
[3]
on page 4 for differences between the 68300C/01C and 68320C/321C pinouts for the 56-pin packages. For information
SSOP
N/A
N/A
N/A
N/A
56
10
11
12
13
14
15
16
17
18
19
20
21
6
7
8
9
GND (RESERVED)
PWR500#
Pin Name
XTALOUT
(PU 10K)
DMINUS
DMARQ
SYSIRQ
XTALIN
DPLUS
IORDY
AGND
AV
GND
GND
GND
GND
GND
V
V
V
NC
CC
CC
CC
CC
[2]
PWR
PWR
PWR
PWR
Type
GND
GND
GND
GND
GND
Xtal
Xtal
Pin
I/O
I/O
I
I
O
[1]
[1]
I
Default State
at Startup
Input
Input
Input
Hi-Z
Hi-Z
Xtal
Xtal
V
Ground.
ATA control. Apply a 1k pull up to 3.3V.
ATA control.
Ground.
Analog V
possible.
24 MHz crystal output. (See
page 12).
24 MHz crystal input. (See
page 12).
Analog ground. Connect to ground with as short a
path as possible.
No connect.
V
USB D+ signal (See
USB D–signal (See
Ground.
V
Ground.
USB interrupt request. (See
Active HIGH. Connect to GND if functionality is not
used.
Ground.
bMaxPower request granted indicator. (See
“PWR500#”
N/A for CY7C68320C/CY7C68321C 56-pin packages.
Reserved. Tie to GND.
CC
CC
CC
. Connect to 3.3V power source.
. Connect to 3.3V power source.
. Connect to 3.3V power source.
CC
. Connect to V
on page 14). Active LOW.
CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
Pin Description
“DPLUS, DMINUS”
“DPLUS, DMINUS”
“VBUS_ATA_ENABLE”
CC
“XTALIN, XTALOUT”
through the shortest path
“XTALIN, XTALOUT”
“SYSIRQ”
on page 13).
on page 12).
on page 12).
on page 14.
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