CY7C68320-56LFXC Cypress Semiconductor Corp, CY7C68320-56LFXC Datasheet

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CY7C68320-56LFXC

Manufacturer Part Number
CY7C68320-56LFXC
Description
IC USB 2.0 BRIDGE AT2LP 56VQFN
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB AT2LP™r
Datasheet

Specifications of CY7C68320-56LFXC

Controller Type
USB 2.0 Controller
Interface
I²C
Voltage - Supply
3.15 V ~ 3.45 V
Current - Supply
50mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
For Use With
CY4615B - KIT USB TO ATA REFERENCE DESIGN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Cypress Semiconductor Corporation
Document 38-08033 Rev. *D
1.0
2.0
• Fixed-function mass storage device—requires no firmware
• Two power modes: Self-powered and USB bus-powered to
• Certified compliant for USB 2.0 (TID# 40460273), the USB
• Operates at high (480-Mbps) or full (12-Mbps) speed USB
• Complies with ATA/ATAPI-6 specification
• Supports 48-bit addressing for large hard drives
• Supports ATA security features
• Supports all ATA commands via ATACB function
• Supports mode page 5 for BIOS boot support
• Supports ATAPI serial number VPD page retrieval for Digital
• Supports PIO modes 0, 3, 4, multiword DMA mode 2, and
• Uses one external serial EEPROM for storage of USB
• ATA interface IRQ signal support
• Support for one or two ATA/ATAPI devices
code
enable bus powered CF readers and truly portable USB
hard drives
Mass Storage Class, and the USB Mass Storage Class
Bulk-Only Transport (BOT) Specification
Rights Management (DRM) compatibility
UDMA modes 2, 3, 4
descriptors and device configuration data
CY7C68320/CY7C68321)
Features (CY7C68300B/CY7C68301B and
Block Diagram
VBUS
XTAL
MHz
24
D+
D-
EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge
USB 2.0 XCVR
SDA
SCL
PLL
3901 North First Street
Figure 2-1. Block Diagram
I2C Bus Controller
CY Smart USB
FS/HS Engine
Internal Control Logic
1.1
1.2
• Support for CompactFlash and one ATA/ATAPI device
• Can place the ATA interface in high-impedance (Hi-Z) to
• Support for board-level manufacturing test via USB
• Low-power 3.3V operation
• Fully compatible with native USB mass storage class drivers
• Cypress mass storage class drivers available for Windows
• Supports HID interface or custom GPIOs to enable features
• Lead-free 56-pin QFN and 100-pin TQFP packages
• CY7C68321 is ideal for battery-powered designs
• CY7C68320 is ideal for self- and bus-powered designs
• Pin-compatible with CY7C68300A (using Backward
• Lead-free 56-pin SSOP and 56-pin QFN packages
• CY7C68301B is ideal for battery-powered designs
• CY7C68300B is ideal for self- and bus-powered designs
allow sharing of the ATA bus with another controller (e.g.,
an IEEE-1394 to ATA bridge chip or MP3 Decoder)
interface
(98SE, ME, 2000, XP) and Mac OS X
such as single button backup, power-off, LED-based notifi-
cation, etc.
Compatibility mode)
4kByte FIFO
Features (CY7C68320/CY7C68321 only)
Features (CY7C68300B/CY7C68301B only)
Control
Data
San Jose
CY7C68300B/CY7C68301B
Misc control signals
Interface
Logic
ATA
CY7C68320/CY7C68321
,
CA 95134
16 Bit ATA Data
Control Signals
ATA Interface
Revised February 21, 2005
408-943-2600

Related parts for CY7C68320-56LFXC

CY7C68320-56LFXC Summary of contents

Page 1

... LED-based notifi- cation, etc. • Lead-free 56-pin QFN and 100-pin TQFP packages • CY7C68321 is ideal for battery-powered designs • CY7C68320 is ideal for self- and bus-powered designs 1.2 Features (CY7C68300B/CY7C68301B only) • Pin-compatible with CY7C68300A (using Backward Compatibility mode) • ...

Page 2

... Specifically, the CY7C68300B/CY7C68301B includes a mode that makes it pin-for-pin compatible with the EZ- USB AT2 (CY7C68300A). The USB port of the CY7C68300B/301B and CY7C68320/321 (AT2LP) are connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the AT2LP and receives status and data from the AT2LP using standard USB protocol ...

Page 3

... DD2 DD3 28 Figure 5-2. 56-pin SSOP Pinout (CY7C68300B/CY7C68301B only) Document 38-08033 Rev. *D (ATA_EN) VBUS_ATA_ENABLE (VBUS_PWR_VALID ) DA2 EZ-USB AT2LP CY7C68300B CY7C68301B 56-pin SSOP NOTE: Labels in italics denote pin functionality during CY7C68300A compatibility mode. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 DD12 56 DD11 55 DD10 54 DD9 53 DD8 52 51 VCC 50 ...

Page 4

... GND 12 NOTE: Italic labels denote pin functionality (PU 10K) PWR500# 13 GND 14 Figure 5-3. 56-pin QFN Pinout (CY7C68300B/CY7C68301B) Document 38-08033 Rev. *D EZ-USB AT2LP CY7C68300B CY7C68301B 56-pin QFN during CY7C68300A compatibility mode. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 42 RESET# 41 GND 40 ARESET# 39 DA2 ( VBUS_PWR_VALID) 38 CS1# 37 CS0# 36 DRVPWRVLD (DA2 ) 35 DA1 ...

Page 5

... IORDY 1 DMARQ 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 VCC 7 DPLUS 8 DMINUS 9 GND 10 VCC 11 GND 12 GPIO1 13 GND 14 Figure 5-4. 56-pin QFN Pinout (CY7C68320/CY7C68321) Document 38-08033 Rev. *D EZ-USB AT2LP CY7C68320 CY7C68321 56-pin QFN CY7C68300B/CY7C68301B CY7C68320/CY7C68321 42 RESET# 41 GND 40 ARESET# 39 DA2 38 CS1# 37 CS0# 36 GPIO0 35 DA1 34 DA0 33 INTRQ ...

Page 6

... DMINUS 18 GND 19 VCC 20 GND 21 SYSIRQ 22 GND 23 GND 24 25 GND PWR500# 26 GND SCL 29 30 SDA Figure 5-5. 100-pin TQFP Pinout (CY7C68320/CY7C68321 only) Document 38-08033 Rev. *D CY7C68300B/CY7C68301B VBUS_ATA_ENABLE EZ-USB AT2LP CY7C68320B CY7C68321B 100-pin TQFP CY7C68320/CY7C68321 DD8 80 79 VCC 78 RESET GND 75 ARESET# 74 DA2 73 CS1# 72 ...

Page 7

... A ‘#’ sign after the pin name indicates that it is active LOW. 3. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320/CY7C68321. Document 38-08033 Rev. *D between the 68300B/01B and 68320/321 pinouts for the 56- pin packages ...

Page 8

... Bus-powered operation selector. Used in systems that are capable of being bus or self-powered to indicate the current power mode Connect. GND Ground. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Pin Description 2 C interface (see section 5.3.2 interface (see section 5.3.2). . Connect to 3.3V power source. . Connect to 3.3V power source. . Connect to 3.3V power source. ...

Page 9

... General purpose I/O pins (see section 5.3.6). The GPIO pins must be tied to GND if functionality is not utilized. If the hs_indicator config bit is set, the GPIO2_nHS pin will reflect the operating speed: ‘1’ = full-speed operation. ‘0’ = high-speed operation. GND Ground. [1] I/O Hi-Z ATA Data bit 12. CY7C68320/CY7C68321 Pin Description Page ...

Page 10

... Figure 5-7 depicts the latching algorithm incorporated by AT2LP. The SYSIRQ pin must be tied low if the HID function is used (refer to Section 6.0). 24MHz Xtal XTALIN Figure 5-6. XTALIN / XTALOUT Diagram CY7C68300B/CY7C68301B CY7C68320/CY7C68321 12pF XTALOUT USB Interrupt Data Byte Page ...

Page 11

... USB specification. Also, If EEPROM byte 8, bit 4 is ‘0’, the ATA interface pins will be placed in a high impedance (Hi-Z) state when VBUS_ATA_ENABLE is ‘0’. If EEPROM byte 8, bit 4 is ‘1’, the ATA interface pins will still be driven when VBUS_ATA_ENABLE is ‘0’. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 No SYSIRQ=1? Yes Latch State of IO Pins Yes ...

Page 12

... AT2 ™ www.cypress.com for more information. 6.0 Cypress’ CY7C68320/CY7C68321 introduces the capability to support Human Interface Device (HID) signaling to the host for such functions as buttons. The ability to add buttons to a mass storage solution opens new applications for backup and other device-side notification to the host. ...

Page 13

... Bit 2 PollAltStatOverride – This bit determines whether or not the Alternate Status register will be polled and the BSY bit will be used to qualify the ATACB operation The AltStat register will be polled until BSY=0 before proceeding with the ATACB operation 1 = The ATACB operation will be executed without polling the AltStat register. CY7C68320/CY7C68321 Page ...

Page 14

... ATACB Address Offset 0x08 (0x1F3) – Sector Number ATACB Address Offset 0x09 (0x1F4) – Cylinder Low ATACB Address Offset 0x0A (0x1F5) – Cylinder High ATACB Address Offset 0x0B (0x1F6) – Device ATACB Address Offset 0x0C (0x1F7) – Command These bytes must be set to 0x00 for ATACB commands. CY7C68320/CY7C68321 Page ...

Page 15

... If no EEPROM is detected, the AT2LP uses a VID/PID of 0x00/0x00. This is not a valid mode of operation. • invalid EEPROM signature is read, the AT2LP defaults into Board Manufacturing Test Mode. There is an additional method available to put the AT2LP into Board Manufacturing Test Mode to allow reprogramming of CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Mode No Test Mode Page ...

Page 16

... CBW (refer to Table 8-1). The type/direction of the command will be determined by the direction bit specified in byte 12, bit 7 (bmCBWFlags) of the CBW (refer to Table 8-1). Bits DCBWSignature dCBWTag dCBWDataTransferLength bwCBWFLAGS Reserved (0) CBWCB (CfgCB or MfgCB CY7C68300B/CY7C68301B CY7C68320/CY7C68321 CfgCB Length specified in bytes Reserved (0) bCBWLUN bCBWCBLength Bits ...

Page 17

... Test Mode operation. See Table 8-5 for an explanation of the mfg_read data format. The data length shall always be eight bytes Table 8-5. Mfg_read Data Format Byte CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Bit(s) Function 7:0 DD[7:0] 7:0 DD[15:8] 7:6 Reserved 5:0 GPIO Output Enable [5:0] 7:6 Reserved 5:0 GPIO Output Data [5:0] 7:0 Reserved ...

Page 18

... A1=0, A2=1) for memories that are internally byte- addressed memories. Note: Devices running in Backward Compatibility Mode should use the 68300A EEPROM organization, and not the 68300B/301B/320/321 format shown in this document. Figure 8-2. “AT2LP Blaster” Tool Screen CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Page ...

Page 19

... ARESET# during any initialization other than power up. Do not set SRST to 0 and Skip Pin Reset the same time Allow ARESET# assertion for all resets Disable ARESET# assertion except for power-on reset cycles. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents 0x53 0x4B ...

Page 20

... CF readers) will set this bit to 0. Systems with one removable device and one non- removable device will set this bit to 1. Bit (5) Package Select. Set this bit to 1 when using the 100-pin device. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents 0xD4 0x07 ...

Page 21

... This bit tells the AT2LP if the UDMA lines are connected to the removable-media device. Bit (2) If bits 1 and 2 are both 0, the number of logical units will be determined by searching the ATA and CF buses for devices. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents 0x00 ...

Page 22

... Length of device descriptor in bytes. Type Descriptor type. USB Specification release number in BCD. USB Specification release number in BCD. Device class. Device subclass. Device protocol. USB packet size supported for default pipe. Number of configurations supported. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents 0x00 0x12 0x01 0x00 0x02 ...

Page 23

... This is an Out endpoint, endpoint number 2. This is a bulk endpoint. Max data transfer size set by speed (Full speed 0x0040; High speed 0x0200) High-speed interval for polling (maximum NAK rate). Set to zero for full speed. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents 0x00 0x09 ...

Page 24

... Interval for polling (max. NAK rate). Length of HID descriptor Descriptor Type HID HID Class Specification release number (1.10) Country Code Number of class descriptors (1 report descriptor) Descriptor Type Length of HID report descriptor Vendor defined - FFA0 CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents 0x07 0x05 0x88 0x02 0x00 ...

Page 25

... Value used to select an alternate setting for the interface identified in prior field Number of endpoints used by this interface (excluding endpoint 0) that are CSM dependent Must be set to zero Must be set to zero Index of a string descriptor that describes this Interface CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents 0x09 0xA5 0xA1 ...

Page 26

... Descriptor type. Language supported. The CY7C68300B supports one LANGID value. String descriptor length in bytes (including bLength). Descriptor type. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents 0x09 0x22 0x00 0x06 0x23 ...

Page 27

... Unicode character MSB. Unicode character LSB. Unicode character MSB. String descriptor length in bytes (including bLength). Descriptor type. Unicode character LSB. Unicode character MSB. Unicode character LSB. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents “p” 0x70 0x00 “r” 0x72 0x00 “e” 0x65 0x00 “ ...

Page 28

... Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. Unicode character LSB. Unicode character MSB. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents 0x00 “B” 0x42 0x00 “2” 0x32 0x00 “ ...

Page 29

... ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character ASCII Character Amount of unused ROM space will vary depending on strings. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 Required Suggested Contents Contents “A” 0x41 0x00 “B” 0x42 0x00 “C” 0x43 “y” 0x79 “ ...

Page 30

... Temperature Under Bias) ............. 0°C to +70°C A Supply Voltage ...........................................+3.15V to +3.45V 2 Ground Voltage ................................................................. 0V C memory device) F (Oscillator or Crystal Frequency) .... 24 MHz ± 100 ppm, osc .................................................................. Parallel Resonant CY7C68300B/CY7C68301B CY7C68320/CY7C68321 wIndex wLength Data Data Length Configuration Data Configuration Data Configuration bytes, addresses 0x0 – 0xF only 2 ...

Page 31

... USB Transceiver Complies with the USB 2.0 specification. 13.0 Ordering Information Part Number CY7C68300B-56PVXC CY7C68301B-56PVXC CY7C68300B-56LFXC CY7C68301B-56LFXC CY7C68320-56LFXC CY7C68321-56LFXC CY7C68320-100AXC CY7C68321-100AXC CY4615B Note: 4. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320/CY7C68321. Document 38-08033 Rev. *D Conditions 0 < ...

Page 32

... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Figure 14-1. 100-lead Thin Plastic Quad Flatpack ( 1.4 mm) Document 38-08033 Rev. *D CY7C68300B/CY7C68301B CY7C68320/CY7C68321 51-85050-*A Page ...

Page 33

... SIDE VIEW 0.08[0.003] C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.30[0.012] 0.50[0.020] 0°-12° C SEATING PLANE Figure 14-3. 56-Lead QFN LF56A CY7C68300B/CY7C68301B CY7C68320/CY7C68321 51-85062-*C BOTTOM VIEW 0.18[0.007] 0.28[0.011] PIN1 ID N 0.20[0.008 0.45[0.018] E-PAD (PAD SIZE VARY BY DEVICE TYPE) 0.24[0.009] (4X) ...

Page 34

... Solder Mask Cu Fill Cu Fill 0.013” dia This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 16-2. Plot of the Solder Mask (White Area) CY7C68300B/CY7C68301B CY7C68320/CY7C68321 PCB Material Page ...

Page 35

... EZ-USB AT2LP, EZ-USB AT2, EZ-USB FX2 and EZ-USB TX2 are trademarks, and EZ-USB is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trade- marks of their respective holders. CY7C68300B/CY7C68301B CY7C68320/CY7C68321 C components from Cypress or one of its sub Standard Page ...

Page 36

... Document History Page Description Title: CY7C68300B/CY7C68301B/CY7C68320/CY7C68321 EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge Document Number: 38-08033 REV. ECN NO. Issue Date ** 129739 12/04/03 *A 215125 SEE ECN *B 274109 SEE ECN *C 318133 SEE ECN *D 323408 SEE ECN Document 38-08033 Rev. *D Orig. of Change GIR New data sheet ...

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