CY7C68320C-100AXC Cypress Semiconductor Corp, CY7C68320C-100AXC Datasheet - Page 40

• Manufacturer Part Number: CY7C68320C-100AXC
• Description: IC USB 2.0 BRIDGE AT2LP 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB AT2LP™r
• Type: USB to ATA Bridger

Specifications of CY7C68320C-100AXC

• Package / Case: 100-LQFP
• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Operating Supply Voltage: 3.3 V
• Supply Current: 50 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4615B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2267; CY7C68320C-100AXC

General PCB Layout Recommendations for
USB Mass Storage Designs
The following recommendations must be followed to ensure
reliable high-performance operation:
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Document 001-05809 Rev. *B
Use at least a four-layer, impedance controlled board to
maintain signal quality.
Specify specific impedance targets (ask your board vendor
what they can achieve).
Maintain uniform trace widths and trace spacing to control
impedance.
Minimize reflected signals by avoiding using stubs and vias.
Connect the USB connector shell and signal ground as near to
the USB connector as possible.
Use bypass/flyback capacitors on VBUS near the connector.
Keep DPLUS and DMINUS trace lengths to within 2 mm of
each other in length, with a preferred length of 20–30 mm.
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to be split under these traces.
Do not place vias on the DPLUS or DMINUS trace routing for
a more stable design.
Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
Source for recommendations:
❐
❐
EZ-USB FX2LP PCB Design Recommendations
High speed USB Platform Design Guidelines
www.cypress.com/?docID=4696
http://www.usb.org/developers/
docs/hs_usb_pdg_r1_0.pdf
Via hole for thermally connecting the
QFN to the circuit board ground plane.
PCB Material
Figure 16. Cross-Section of the Area Under the QFN Package
Cu Fill
Solder Mask
0.013” dia
0.017” dia
Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good thermal
bond to the circuit board. A Copper (Cu) fill must be designed
into the PCB as a thermal pad under the package. Heat is trans-
ferred from the AT2LP through the device’s metal paddle on the
bottom side of the package. Heat from here is conducted to the
PCB at the thermal pad. It is then conducted from the thermal
pad to the PCB inner ground plane by a 5 x 5 array of vias. A via
is a plated through-hole in the PCB with a finished diameter of
13 mil. The QFN’s metal die paddle must be soldered to the
PCB’s thermal pad. Solder mask is placed on the board top side
over each via to resist solder flow into the via. The mask on the
top side also minimizes outgassing during the solder reflow
process.
For further information on this package design, refer to the appli-
cation note Surface Mount Assembly of AMKOR’s MicroLead-
Frame (MLF) Technology. The application note provides detailed
information on board mounting guidelines, soldering flow, rework
process, etc.
Figure 16
package. The cross section is of only one via. The solder paste
template needs to be designed to enable at least 50% solder
coverage. The thickness of the solder paste template must be
5 mil. It is recommended that ’No Clean,’ type 3 solder paste is
used for mounting the part. Nitrogen purge is recommended
during reflow.
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
Cu Fill
PCB Material
displays a cross-sectional area underneath the
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