CY7C68320C-100AXC Cypress Semiconductor Corp, CY7C68320C-100AXC Datasheet - Page 23

• Manufacturer Part Number: CY7C68320C-100AXC
• Description: IC USB 2.0 BRIDGE AT2LP 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB AT2LP™r
• Type: USB to ATA Bridger

Specifications of CY7C68320C-100AXC

• Package / Case: 100-LQFP
• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Operating Supply Voltage: 3.3 V
• Supply Current: 50 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4615B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2267; CY7C68320C-100AXC

Table 11. Configuration Data Organization (continued)
Document 001-05809 Rev. *B
0x06
0x07
Address
Byte
SRST Enable
Skip Pin Reset
ATA UDMA Enable
ATAPI UDMA Enable
UDMA Modes
Reserved
Multi-word DMA mode
PIO Modes
Configuration
Item Name
Bit 1
Determines if the AT2LP is to do an SRST reset during drive
initialization. At least one reset must be enabled. Do not set
SRST to 0 and Skip Pin Reset to 1 at the same time.
0 = Do not perform SRST during initialization.
1 = Perform SRST during initialization.
Bit 0
Skip ARESET# assertion. When this bit is set, the AT2LP
bypasses ARESET# during any initialization other than
power up. Do not set SRST Enable to 0 and Skip Pin Reset
to 1 at the same time.
0 = Allow ARESET# assertion for all device resets.
1 = Disable ARESET# assertion except for chip reset cycles.
Bit 7
Enable Ultra DMA data transfer support for ATA devices. If
enabled, and if the ATA device reports UDMA support for the
indicated modes, the AT2LP uses UDMA data transfers at
the highest negotiated rate possible.
0 = Disable ATA device UDMA support.
1 = Enable ATA device UDMA support.
Bit 6
Enable Ultra DMA data transfer support for ATAPI devices.
If enabled, and if the ATAPI device reports UDMA support
for the indicated modes, the AT2LP uses UDMA data
transfers at the highest negotiated rate possible.
0 = Disable ATAPI device UDMA support.
1 = Enable ATAPI device UDMA support.
Bits 5:0
These bits select which UDMA modes are enabled. The
AT2LP operates in the highest enabled UDMA mode
supported by the device. The AT2LP supports UDMA modes
2, 3, and 4 only.
Bit 5 = Reserved. Must be set to 0.
Bit 4 = Enable UDMA mode 4.
Bit 3 = Enable UDMA mode 3.
Bit 2 = Enable UDMA mode 2.
Bit 1 = Reserved. Must be set to 0.
Bit 0 = Reserved. Must be set to 0.
Bits 7:3
Must be set to 0.
Bit 2
This bit enables multi-word DMA support. If this bit is set and
the drive supports it, multi-word DMA is used.
Bits 1:0
These bits select which PIO modes are enabled. Setting to
‘1’ enables use of that mode with the attached drive, if the
drive supports it. Multiple bits may be set. The AT2LP
operates in the highest enabled PIO mode supported by the
device. The AT2LP supports PIO modes 0, 3, and 4 only.
PIO mode 0 is always enabled and has no corresponding
configuration bit.
Bit 1 = Enable PIO mode 4.
Bit 0 = Enable PIO mode 3.
Item Description
Configuration
CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
Required
Contents
Contents
Variable
Page 23 of 42
0xD4
0x07
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