MC68360RC25K Freescale Semiconductor, MC68360RC25K Datasheet - Page 676
MC68360RC25K
Manufacturer Part Number
MC68360RC25K
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360RC25K
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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Parallel Interface Port (PIP)
FC3-0 —Function Code 3-0
MOT—Motorola
Res—Reserved. Should be set to zero by the user.
7.13.8.16 RECEIVER BUFFER DESCRIPTOR POINTER (RBPTR). The receiver buffer
descriptor pointer (RBPTR) points to the next BD that the receiver will transfer data to when
it is in IDLE state, or to the current BD during frame reception. After a reset or when the end
of BD table is reached, the CP initializes this pointer to the value programmed in the RBASE
entry. Although RBPTR need never be written by the user in most applications, it may be
modified by the user when the receiver is disabled.
7.13.8.17 CENTRONICS RECEIVER PROGRAMMING MODEL. The host configures the
PIP to operate as a Centronics controller by programming the PIP Configuration register
(PIPC). Timing attributes (ACK pulse width and the timing between ACK and BUSY) are set
by programming the PIP Timing Parameters register (PTPR). The receive errors are
reported through the Rx BD.
7.13.8.18 CENTRONICS CONTROL CHARACTERS. The Centronics receiver has the
capability to recognize special control characters. These characters may be used when the
Centronics functions in a message oriented environment. Up to eight control characters may
be defined by the user in the Control Characters Table. Each of these characters may be
either written to the receive buffer (upon which the buffer is closed and a new receive buffer
taken) or rejected. If rejected, the character is written to the Received Control Character
Register (RCCR) in internal RAM and a maskable interrupt is generated. This method is
useful for notifying the user of the arrival of control characters that are not part of the
received messages.
The Centronics receiver uses a table of 16-bit entries to support control character recogni-
tion. Each entry consists of the control character, a valid bit, and a reject character bit.
7-352
These bits contain the function code value used during this SDMA channel’s memory ac-
cesses. It is suggested that the user write bit FC3 with a one to identify this SDMA channel
access as a DMA-type access. Example: FC3-FC0 = 1000 (binary). Do not write the value
0111 (binary) to these bits.
This bit should be set by the user to achieve normal operation.
0 = DEC (and Intel) convention is used for byte ordering. Swapped operation. Also
1 = Motorola byte ordering. Normal operation. Also called big-endian byte ordering. As
called little-endian byte ordering. The bytes stored in each buffer word are reversed
as compared to the Motorola mode.
data is received from the serial line and put into the buffer, the most significant byte
of the buffer word contains data received earlier than the least significant byte of
the same buffer word.
RES
Freescale Semiconductor, Inc.
7
For More Information On This Product,
RES
6
MC68360 USER’S MANUAL
Go to: www.freescale.com
RES
5
MOT
4
3
2
FC3–FC0
1
0
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