MC68360RC25K Freescale Semiconductor, MC68360RC25K Datasheet - Page 678
MC68360RC25K
Manufacturer Part Number
MC68360RC25K
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360RC25K
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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Parallel Interface Port (PIP)
RCCR—Received Control Character Register
7.13.8.19 CENTRONICS SILENCE PERIOD. The Centronics controller may be pro-
grammed to close the receive data buffer after a programmable silence period. The length
of the silence period is determined by the MAX_SL register value. The centronics controller
will decrement the MAX_SL value every 1024 system clocks. If it reaches zero before any
data received, the receive buffer will be closed automatically. Setting MAX_SL value to zero
disables this function.
7.13.8.20 CENTRONICS RECEIVER COMMAND SET.
7.13.8.20.1 INIT RX PARAMETERS Command. Initializes all the receive parameters in
the Centronics parameter RAM to their reset state. This command should only be issued
when the receiver is disabled.
7.13.8.20.2 CLOSE RX BD Command. The CLOSE RX BD command is used to force the
Centronics controller to close the current receive BD if it is currently being used and to use
the next BD in the list for any subsequent data that is received. If the Centronics controller
is not in the process of receiving data, no action is taken by this command.
7.13.8.21 RECEIVER ERRORS.
7.13.8.21.1 Buffer Descriptor Busy. This error occurs if a character was received from the
Centronics interface and the current BD that should be processed by the Centronics control-
ler is not empty (E bit in the BD = 0). The channel will resume reception after the s/w pre-
pares the BD.
7.13.8.22 CENTRONICS RECEIVE BUFFER DESCRIPTOR. The CP confirms transmis-
sion (or indicates error conditions) via the buffer descriptors to inform the processor that the
buffers have been serviced.
E—Empty
7-354
Upon a control character match for which the Reject bit is set, the Centronics will write the
control character into the RCCR and generate a maskable interrupt. The core must pro-
cess the interrupt and read the RCCR before a second control character arrives. Failure
to do so will result in the Centronics overwriting the first control character.
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
0 = The data buffer associated with this BD has been filled with received data, or data
1 = The data buffer associated with this BD is empty, or reception is currently in
reception has been aborted due to an error condition. The core is free to examine
or write to any fields of this Rx BD. The CP will not use this BD again while the emp-
ty bit remains zero.
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E bit is set, the CPU32+ core should not write any fields of this Rx BD.
15
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Freescale Semiconductor, Inc.
For More Information On This Product,
12
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11
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MC68360 USER’S MANUAL
Go to: www.freescale.com
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CM
TX DATA BUFFER POINTER
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DATA LENGTH
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