MC68360RC25K Freescale Semiconductor, MC68360RC25K Datasheet - Page 209
MC68360RC25K
Manufacturer Part Number
MC68360RC25K
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360RC25K
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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the bus is not being monitored. Each method requires a slightly different serial logic design
to avoid spurious serial clocks.
Figure 5-24 represents the timing required for asserting BKPT during a single bus cycle.
Figure 5-25 depicts the timing of the BKPT/FREEZE method. In both cases, the serial clock
is left high after the final shift of each transfer. This technique eliminates the possibility of
accidentally tagging the prefetch initiated at the conclusion of a BDM session. As mentioned
previously, all timing within the CPU is derived from the rising edge of the clock; the falling
edge is effectively ignored.
Figure 5-26 represents a sample circuit providing for both BKPT assertion methods. As the
name implies, FORCE_BGND is used to force a transition into BDM by the assertion of
BKPT. FORCE_BGND can be a short pulse or can remain asserted until FREEZE is
asserted. Once asserted, the set-reset latch holds BKPT low until the first SHIFT_CLK is
applied.
FORCE_BGND
FORCE_BGND
BKPT_TAG
BKPT_TAG
SHIFT_CLK
SHIFT_CLK
FREEZE
FREEZE
BKPT
BKPT
Figure 5-24. BKPT Timing for Single Bus Cycle
FORCE_BGND
SHIFT_CLK
Figure 5-25. BKPT Timing for Forcing BDM
BKPT_TAG
Figure 5-26. BKPT/DSCLK Logic Diagram
Freescale Semiconductor, Inc.
RESET
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
S2
R
S1
Q
Q
BKPT/DSCLK
CPU32+
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