MC68360RC25K Freescale Semiconductor, MC68360RC25K Datasheet - Page 746
MC68360RC25K
Manufacturer Part Number
MC68360RC25K
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360RC25K
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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Applications
The MC68302 TCNx register is the same as the QUICC TCNx.
The MC68302 TERx register is the same as the QUICC TERx.
WATCHDOG TIMER
The MC68302 timer 3 is called the watchdog timer. This software watchdog timer must be
serviced periodically or can be used to generate a system reset. The software watchdog
timer on the QUICC exists in the SIM60. It corresponds to the software watchdog available
on other members of the MC68300 family.
The WRR and WCN on the MC68302 do not have direct counterparts on the QUICC. To
program the software watchdog on the QUICC, the user should initially program the SYPCR,
the SWIV (optional), and service the software watchdog using the SWSR. Additionally, an
indication of a software watchdog reset may be found in the RSR.
9.3.4.4 INTERNAL REGISTERS (COMMUNICATION PROCESSOR). The following para-
graphs detail the registers associated with the communications processor, according to their
ascending order in the MC68302 memory map. Note that the address offsets of the QUICC
registers are different than the offsets on the MC68302 registers.
The 8-bit command register (CR) also exists on the QUICC, but it is expanded to 16 bits.
SCCs
The MC68302 SCC registers are mapped to the QUICC as follows.
The SCONx register controls the clocking scheme and baud rates of the MC68302 SCCs.
On the QUICC, four independent baud rate generators that are not associated with specific
SCCs are available. Therefore, this register is implemented in the QUICC baud rate gener-
ator and is called the BRGC. Note that the BRGC contains new bits, including a reset bit and
an enable bit.
9-26
The FLG bit still exists in the same location of the QUICC CR.
The two CH NUM bits have been shifted to bit locations 7 and 6 and expanded to four bits
rather than two (bits 6 and 5 also), since more peripherals may now receive commands.
If bits 6 and 5 are cleared, the SCC channel number encodings are compatible from the
MC68302 to the QUICC.
The two OPCODE bits have been increased to four bits, shifted left in the register, and
redefined to include many more commands. However, the original commands available
on the MC68302 are still available.
The RST bit is shifted to become bit 15 of the QUICC CR. To reset the MC68302, the val-
ue $81 was issued to the CR. To reset the QUICC, the value $8001 is issued to the CR.
The DIV4 bit is now a divide-by-16 option and is implemented in the DIV16 bit of the
QUICC BRGC.
The CD10–CD0 bits become CD11–CD0 and are located in the QUICC BRGC.
The RCS bit is implemented in the bank of clocks control in the three RxCS bits of the
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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