MC68360RC25K Freescale Semiconductor, MC68360RC25K Datasheet - Page 315
MC68360RC25K
Manufacturer Part Number
MC68360RC25K
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360RC25K
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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WP—Write Protection
PAREN—Parity Checking Enable
CSNTQ—CS Negate Timing QUICC (SRAM Bank Only)
CSNT40—CS Negate Timing MC68EC040 (SRAM Bank Only)
This bit can restrict write accesses within the address range of a BR. An attempt to write
to the range of addresses specified in a BR that has this bit set can cause the BERR signal
to be asserted by the bus monitor logic (if enabled), causing termination of this cycle.
This bit is used to enable checking of parity on either an SRAM or DRAM bank.
This bit is used to determine when CS is negated during an internal QUICC or external
QUICC/MC68030-type bus master write cycle. This is helpful to meet address/data hold
time requirements for slow memories and peripherals (see Figure 6-13 and Figure 6-14).
This bit is used to determine when CS is negated during an MC68EC040 write cycle. This
is helpful to meet address/data hold time requirements (see Figure 6-15).
0 = This DRAM/SRAM bank is invalid.
1 = This DRAM/SRAM bank is valid.
0 = Both read and write accesses are allowed.
1 = Only read accesses are allowed. The RAS/CS signal, TA, and DSACK will not be
0 = Parity checking is disabled.
1 = Parity checking is enabled.
0 = CS is negated normally (as late as possible).
1 = CS is negated one phase earlier, but the cycle length is not affected.
0 = CS is negated normally (as late as possible).
1 = CS is negated one phase earlier, but the cycle length is not affected.
asserted by the QUICC on write cycles to this memory bank. WPER will be set in
the MSTAT register if a write to this memory bank is attempted.
An access to a region that has no V-bit set may cause a bus
monitor timeout.
Following a system reset, the V-bit is set in BR0 if the global chip
select is enabled. See the CONFIG pins for more details.
Parity checking is not possible for asynchronous external mas-
ters.
CSNTQ is ignored for an SRAM cycle by an external master if
the SYNC bit is cleared. CSNTQ = 1 is not valid for external
DSACK assertion
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE
NOTE
NOTE
System Integration Module (SIM60)
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