MC68360RC25K Freescale Semiconductor, MC68360RC25K Datasheet - Page 568
MC68360RC25K
Manufacturer Part Number
MC68360RC25K
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360RC25K
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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RSTRT
RRJCT
Serial Communication Controllers (SCCs)
The CAM control logic uses RSTRT, in combination with the RXD and RCLK signals, to
store the destination address, source address, etc. and generate writes to the CAM for
address recognition. In addition, the RENA signal supplied from the EEST may be used to
abort the comparison if a collision occurs on the receive frame.
After the comparison occurs, the CAM control logic asserts the receive reject (RRJCT) pin,
if the current receive frame should be rejected. The QUICC Ethernet controller will then
immediately stop writing data to system memory and will reuse the buffer(s) for the next
frame. If the CAM wishes to accept the frame, the CAM control logic does nothing (RRJCT
is not asserted). If RRJCT is asserted, it must be asserted prior to the end of the receive
frame.
7-244
RXD
NOTE: The receive data is sent directly from the EEST serial interface to the CAM using RXD and RCLK. RSTRT is asserted
at the beginning of the destination address. RRJCT should be asserted during the frame to cause the frame to be rejected.
The system bus is used for CAM initialization and maintenance.
PREAMBLE
7 BYTES
SYSTEM BUS
ADDRESS BIT FOR A DURATION OF ONE
ASSERTED ON SECOND DESTINATION
Figure 7-68. QUICC Ethernet Serial CAM Interface
DELIMITER
1 BYTE
FRAME
START
Freescale Semiconductor, Inc.
BIT TIME.
SDACK2–SDACK1
For More Information On This Product,
6 BYTES
QUICC
ADDR.
DEST.
SCC
PARALLEL I/O
TCLK (CLKx)
RCLK (CLKx)
FRAME TAG
TENA (RTS)
CLSN (CTS)
OPTIONAL
RENA (CD)
PB15–PB8
MC68360 USER’S MANUAL
BYTE
Go to: www.freescale.com
RSTRT
RRJCT
RxD
TxD
6 BYTES
SOURCE
ADDR.
SHIFT REGISTER
CAM CONTROL
2 BYTES
LENGTH
TYPE/
AND
FRAME REJECTED IF ASSERTED DURING FRAME RECEPTION.
RX
RENA
RCLK
CLSN
LOOP
TX
TENA
TCLK
FURTHER TRANSMISSIONS ON SYSTEM BUS CEASE, AND
MC68160
EEST
46–1500 BYTES
BUFFER DESCRIPTORS ARE REUSED.
DATA
CAM
TO MEDIA
SEQUENCE
4 BYTES
FRAME
CHECK
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