MC68360RC25K Freescale Semiconductor, MC68360RC25K Datasheet - Page 286
MC68360RC25K
Manufacturer Part Number
MC68360RC25K
Description
IC MPU QUICC 25MHZ 241-PGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360RC25K
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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System Integration Module (SIM60)
tial general system clock of 13.14 MHz. The user would then write the MF bits to raise this
frequency to the desired frequency.
6.9.3.11 CLOCK DIVIDER CONTROL REGISTER (CDVCR). The CDVCR controls the
operation of the low-power divider for the various clocks on the QUICC. It can be read or
written only in supervisor mode. Writing this register is allowed only if the CDVWP bit is zero.
The reset state of CDVCR produces the maximum frequency for all the clocks that it affects.
CDVWP—CDVCR Write Protect
DFSY—Division Factor for the SyncCLK
DFTM—Division Factor for the BRGCLK
INTEN—Interrupt Enable
6-42
CDVWP
This bit protects accidental writing of the CDVCR. After reset, this bit defaults to zero to
enable writing. Setting this bit prevents further writing (excluding the first write that sets
this bit).
These bits define the SyncCLK frequency. Changing the value of the these bits will not
result in a loss-of-lock condition. These bits are cleared by a hardware reset. The default
value is divide by 1 (VCO/2) which is 25 MHz in a 25-MHz system.
These bits define the BRGCLK frequency. Changing the value of the these bits will not
result in a loss-of-lock condition. These bits are cleared by a hardware reset. The default
value is divide by 1 (VCO/2) which is 25 MHz in a 25-MHz system.
These bits specify if the general system clock returns to high frequency (defined by the
DFNH bits) while the CPU32+ either has a pending interrupt or an interrupt routine in pro-
cess, either of which has a level higher than INTEN2–INTEN0. To prevent interrupts from
causing the general system clock to automatically switch to high frequency, write INTEN
with 111.
15
0
00 = Divide by 1 (normal operation)
01 = Divide by 4
10 = Divide by 16
11 = Divide by 64
00 = Divide by 1 (normal operation)
01 = Divide by 4
10 = Divide by 16
11 = Divide by 64
14
0
DFSY
SWT clocking does not stop when the PLL is in the process of
acquiring a lock. Therefore, the user should service the SWT (re-
set its count) before and after changing the MF bits.
13
0
12
0
DFTM
Freescale Semiconductor, Inc.
11
0
For More Information On This Product,
10
0
MC68360 USER’S MANUAL
Go to: www.freescale.com
INTEN
9
0
NOTE
8
0
RRQEN
0
7
6
0
DFNL
5
0
4
0
3
0
DFNH
0
2
1
0
CSRC
0
0
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