MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 444

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
The value of the program counter saved in this stack frame is the F-line
operation word address of the coprocessor instruction during which the pri-
the stack frame, an RTE instruction causes the MC68030 to return and rein-
The take pre-instruction exception primitive can be used when the copro-
to the programmer's model, the coprocessor can release the main processor
the command or condition CIR to initiate a general or conditional instruction,
mitive was received. Thus, if the exception handler routine does not modify
itiate execution of the coprocessor instruction.
cessor does not recognize a value written to either its command CIR or
condition CIR to initiate a coprocessor instruction. This primitive can also be
used if an exception occurs in the coprocessor instruction before any pro-
gram-visible resources are modified by the instruction operation. This pri-
an inconsistent state.
One of the most important uses of the take pre-instruction exception primitive
concurrently with the main processor's instruction execution. If the copro-
cessor no longer requires the services of the main processor to complete a
cpGEN instruction and the concurrent instruction completion is transparent
operations concurrently with the main processor operation. If an exception
occurs while the coprocessor is executing an instruction concurrently, the
exception is not processed until the main processor attempts to initiate the
mitive should not be used during a coprocessor instruction if program-visible
resources have been modified by that instruction. Otherwise, since the
MC68030 reinitiates the instruction when it returns from exception process-
ing, the restarted instruction receives the previously modified resources in
is to signal an exception condition in a cpGEN instruction that was executing
by issuing a primitive with CA=O. The main processor usually executes the
next instruction in the instruction stream, and the coprocessor completes its
next general or conditional instruction. After the main processor writes to
it then reads the response CIR. At this time, the coprocessor can return the
SP
Figure 10-41. MC68030 Pre-lnstruction Stack Frame
+02
+06
15
0
14
0
MC68030 USER'S MANUAL
13
0
12
0 I
ll
10
.~=~ ~ C, ~ ',~
9
STATUS REGISTER
8
COUNTER
VECTOR NUMBER
7
6
5
4
3
2
l
0
10-57
10