MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 404

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10.2.2.3 TEST COPROCESSOR CONDITION, DECREMENT AND BRANCH INSTRUC-
10.2.2.3.1 Format.
MOTOROLA
TION.
and a loop counter in the main processor. It is useful for implementing DO-
tion, decrement and branch instruction, denoted by the cpDBcc mnemonic.
The first word of the cpDBcc instruction is the F-line operation word. This
word contains the CplD field in bits [9-11] and 001001 in bits [8:3] to identify
the cpDBcc instruction. Bits [0:2] of this operation word specify the main
The second word of the cpDBcc instruction format contains the coprocessor
the condition ClR to initiate execution of the cpDBcc instruction by the co-
the cpDBcc instruction can include this information in extension words. These
The last word of the instruction contains the displacement for the cpDBcc
instruction is similar to that of the DBcc instruction provided in the M68000
Family instruction set. This operation uses a coprocessor evaluated condition
UNTIL constructs used in many high-level languages.
processor data register used as the loop counter during the execution of the
instruction.
condition selector in bits [0-5] and should contain zeros in bits [6-15] to
maintain compatibility with future M68000 products, This word is written to
processor.
extension words follow the word containing the coprocessor condition se-
lector field in the cpDBcc instruction format.
instruction. This displacement is a twos-complement 16-bit value that is sign-
extended to long-word
If the coprocessor requires additional information to evaluate the condition,
lation.
15
Figure 10-12. Test Coprocessor Condition, Decrement and Branch
14
The
1'1'1'1
operation
13
Figure 10-12 shows the format of the test coprocessor condi-
12
OPTIONAL COPROCESSOR-DEFI N ED EXTENSI O N WORDS
(RESERVED)
11
of the test coprocessor condition, decrement and branch
MC68030 USER'S
Instruction Format (cpDBcc)
size
Cpl O
when it is
9
DI S PLACEMENT
I 0 I 0 I '
8
MANUAL
used
7
in a destination address calcu-
6
0 I 0 I I
5
CONO T ON SELECTOR
4
3
EFFEcT,VEA00RESs
I
2
10-17
0
10