MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 314

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9.2 A D D R E S S T R A N S L A T I O N
9.2.1 General Flow for Address Translation
MOTOROLA
to ATC translation as follows. If the requested access misses in the ATC, the
All long-format descriptors and short-format invalid descriptors include one
or two unused fields. The operating system can use these fields for its own
purposes. For example, the operating system can encode these fields to
specify the type of invalid descriptor. Alternately, the external device address
of a page that is not resident in main memory can be stored in the unused
field.
The function of the MMU is to translate logical addresses to physical ad-
A CPU space address (FC0-FC2 -- $7) is a special case that is immediately
the flowchart applies to CPU space accesses (FC0-FC2 =$7). The next branch
the required data or instruction), no memory access is necessary. The third
entry is created after the table search, and the access is retried. If an access
dresses according to control information stored by the system in the MMU
registers and in translation table trees resident in memory.
used as a physical address without translation. For other accesses, the trans-
lation process proceeds as follows:
Figure 9-8 is a general flowchart for address translation. The top branch of
applies to read accesses only. When either of the on-chip caches hits (contains
branch applies to transparent translation. The bottom three branches apply
memory cycle is aborted, a n d a table search operation proceeds. An ATC
3. Compare the logical address and function code to the tag portions of
4. When no on-chip cache hit occurs (on a read) and no -FI-x register matches
2. Compare the logical address and function code to the transparent trans-
1. Search the on-chip data and instruction caches for the required instruc-
tion word or operand on read accesses.
the entries in the ATC and use the corresponding physical address for
the corresponding physical address from the corresponding translation
tree, create a valid ATC entry for the logical address, and repeat step 3.
or both of the registers match.
the memory access when a match occurs.
or valid ATC entry matches, initiate a table search operation to obtain
lation parameters in the transparent translation registers, and use the
logical address as a physical address for the memory access when one
MC68030 USER'S MANUAL
9-13
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