MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 349

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9
9-48
9.5.5.2 SUPERVISOR TRANSLATION TREE.
9.5.5.3 SUPERVISOR ONLY.
9.5.5.4 WRITE PROTECT.
The subsequent retry of the user access results in a bus error exception being
taken. The S bit can be used to protect the entire area of memory defined in
sequent retry of the write access results in a bus error exception being taken.
The WP bit can be used to protect the entire area of memory defined in a
tree for this technique.
translation tree pointed to by the SRP is selected for all supervisor level
accesses. This translation tree can be common to all tasks. This technique
segments the logical address space into user and supervisor areas without
adding the function code level to the translation trees.
and data without segmenting the logical address space into Supervisor and
user address spaces. The long formats of table descriptors and page de-
scriptors contain S bits to protect areas of memory from access by user
programs. When a table search for a user access encounters an S bit set in
any table or page descriptor, the table search is completed and an ATC
descriptor corresponding to the logical address is created with the B bit set.
a branch of the translation tree or only one or more pages from user program
access.
of the segmented address spaces for programs and data. All table and page
descriptors contain WP bits to protect areas of memory from write accesses
of any kind. When a table search encounters a WP bit set in any table or
page descriptor, the table search is completed and an ATC descriptor cor-
responding to the logical address is created with the WP bit set. The sub-
branch of the translation tree, or only one or more pages from write accesses.
Figure 9-33 shows a memory map of the logical address space organized to
a supervisor translation tree. A supervisor translation tree protects supervisor
programs and data from access by user programs and user programs and
data from access by supervisor programs. Access is granted to the supervisor
programs which can access any area of memory with the move address
space (MOVES) instruction. When the SRE bit in the TC register is set, the
use S and WP bits for protection. Figure 9-34 shows an example translation
The MC68030 provides write protection independently
MC68030 USER'S MANUAL
A third mechanism protects supervisor programs
A second protection mechanism uses
MOTOROLA