MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 148

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
the MC68030 attempts to fill the cache entry. Figure 6-5 shows the organi-
the associated tag corresponds to a long-word entry to be loaded. Since a
The bytes are latched in the following order: b3, b0, bl, and b2. Note that
operation requires two read cycles. The first cycle requests the byte at address
$03. If the device responds with a 16-bit DSACKx encoding, the word at
word are latched, and the cache entry is filled.
When a cachable read cycle provides data with both CIIN and BERR negated,
zation of a line of data in the caches. The notation b0, bl, b2, and so forth
single valid bit applies to an entire long word, a single entry mode operation
operation results in four bus cycles. The first cycle requested by the MC68030
during cache loading operations, devices must indicate the same port size
consistently throughout all cycles for that long-word entry in the cache.
address $02 (including the requested byte) is accepted by the MC68030. The
second cycle requests the word at address $00. Since the device again re-
sponds with a 16-bit DSACKx encoding, the remaining two bytes of the long
identifies the bytes within the line. For each entry in the line, a valid bit in
must provide a full 32 bits of data. Ports less than 32 bits wide require several
read cycles for each entry.
Figure 6-5 shows an example of a byte data operand read cycle starting at
byte address $03 from an 8-bit port. Provided the data item is cachable, this
reads a byte from address $03. The 8-bit DSACKx response causes the
MC68030 to fetch the remainder of the long word starting at address $00.
Figure 6-6 shows the access of a byte data operand from a 16-bit port. This
CYCLE
1
2
3
4
3-BYTE
WORD
BYTE
BYTE
SIZE
Figure 6-5. Single Entry Mode Operation - - 8-Bit Port
ADDRESS
$03
$00
$02
$01
~
$00
MC68030 USER'S MANUAL
~
~ - ]
r ~
$04
_ THIS is THE REQUESTED OPERAND
- tIEXT BYTE FOR COMPLETING CACHE ENTRY
- NEXT BYTE FOR COMPLETING CACHE ENTRY
- ~ST BYTE TO COMPLETE THE LONG WORD
S08
COMMENT
$0C
6-11
6