MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 413

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10
10-26
format word (or a valid format word whose length field is not a multiple of
to be transferred from the coprocessor to the effective address specified. If
the state information is not a multiple of four bytes in size, the MC68030
and writing the information obtained into memory until all the bytes specified
any coprocessor instructions.
The cpSAVE instruction is a privileged instruction. When the main processor
ception processing without accessing any of the coprocessor interface reg-
The MC68030 initiates format error exception processing if it reads an invalid
four bytes) from the save CIR during the execution of a cpSAVE instruction
processor instruction prior to beginning exception processing. Figure 10-16
initiates format error exception processing (refer to 10.5.1.5 FORMAT ER-
RORS). The coprocessor and main processor coordinate the transfer of the
internal state of the coprocessor using the operand CIR. The MC68030 com-
pletes the coprocessor context save by repeatedly reading the operand CIR
in the coprocessor format word have been transferred. Following a cpSAVE
instruction, the coprocessor should be in an idle state - - t h a t is, not executing
identifies a cpSAVE instruction, it checks the supervisor bit in the status
register to determine whether it is operating at the supervisor privilege level.
If the MC68030 attempts to execute a cpSAVE instruction while at the user
privilege level (status register bit [13]=0), it initiates privilege violation ex-
isters (refer to 10.5.2.3 PRIVILEGE VIOLATIONS).
(refer to 10.2.3.2.3 Invalid Format Word). The MC68030 writes an abort mask
(refer to 10.2.3.2.3 Invalid Format Word) to the control CIR to abort the co-
M3
M1
M2
M3
M4
M5
EVALUATE EFFECTIVE ADDRESS SPECIFIED IN F-LINE
IN FORMAT WORO FROM OPERAND ClR TO
RECOGNIZE COPROCESSOR INSTRUCTION F-LINE
OPERATION WORD
READ SAVE CIR TO INITIATE THE cpSAVE INSTRUCTION
IF (FORMAT = NOT READY) DO STEPS 1) AND 2) BELOW
OPWORO AND STORE FORMAT WORD AT
EFFECTIVE ADDRESS
IF (FORMAT = EMPTY) 60 TO M5
ELSE, TRANSFER NUMBER OF BYTES INDICATED
EFFECTIVE ADDRESS
PROCEED WITH EXECUTION OF NEXT INSTRUCTION
2) GO TO M2
1) SERVICE PENDING INTERRUPTS
Figure 10-16. Coprocessor Context Save Instruction Protocol
MAIN PROCESSOR
MC68030 USER'S MANUAL
C3
C1
62
IF (NOT READY TO BEGIN CONTEXT SAVE OPERATION)
O0 STEPS 1) AND 2) BELOW
TRANSFER NUMBER OF BYTES INDICATED IN
PLACE APPROPRIATE FORMAT WORD IN SAVE CIR
FORMAT WORD THROUGH OPERAND CIR
2) SUSPEND OR COMPLETE CURRENT OPERATIONS
1) PLACE NOT READY FORMAT CODE IN SAVE CIR
COPROCESSOR
MOTOROLA