Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 60
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
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UM008101-0601
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
For example, the Z80 DMA can be programmed either to stop, interrupt the
CPU, continue, or repeat a transfer when a target event such as an end-of-
block, byte match, or Ready-line condition is reached. Alternatively, its
buffered address counters can be reloaded during one byte-mode transfer so
that the next transfer can begin quickly at a new location. Also, entire read
and write cycle timings can be modified independently for each port to fit
the requirements of other CPUs, memory, or I/O devices that are faster or
slower than the standard Z80 Family timing.
This topic, as well as the others described earlier, are expanded in following
chapters. They are introduced here to give a generalized framework from
which to launch a more detailed discussion of the Z80 DMA.
(See also Figure 20 through Figure 23).
Figure 17.
YES
(Single)
Request
Transfer
Release
NO
BYTE
Control
Control
Active
RDY
Byte
Modes of Operation
?
YES
(Demand)
NO
BURST
Request
Transfer
Release
Control
Control
Active
Byte
RDY
?
Direct Memory Access
YES
CONTINUOUS
NO
Request
Transfer
Control
(Block)
Active
RDY
Byte
?
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