Z0847006PSG Zilog, Z0847006PSG Datasheet

IC 6MHZ Z80 NMOS DART 40-DIP

Z0847006PSG

Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet

Specifications of Z0847006PSG

Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
Z80 Family
CPU Peripherals
User Manual
UM008101-0601
ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008
Telephone: 408.558.8500 • Fax: 408.558.8300 •
www.ZiLOG.com

Related parts for Z0847006PSG

Z0847006PSG Summary of contents

Page 1

... Z80 Family CPU Peripherals User Manual UM008101-0601 ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com ...

Page 2

... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized ...

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Table of Contents Counter/Timer Channels CTC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Z80 CPU Peripherals User Manual iv Direct Memory Access DMA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Direct Memory Access (continued) Write Register 3 Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Z80 CPU Peripherals User Manual vi Parallel Input/Output (continued) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Synchronous Modes Of Operation . . . . . . . . . . . . . . . . . . . . . . .240 Serial Input/Output (continued) Synchronous Transmit . . . . . . . . ...

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Z80 CPU Peripherals User Manual viii UM008101-0601 Table of Contents ...

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List of Figures Counter/Timer Channels Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. CTC Read Cycle . . . . . . . . . . . . ...

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Z80 CPU Peripherals User Manual x Direct Memory Access (continued) Figure 24. Variable Cycle Length . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Direct Memory Access (continued) Figure 50. CE/WAIT Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Figure 51. Simultaneous Transfer Multiplexer ...

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Z80 CPU Peripherals User Manual xii Direct Memory Access (continued) Figure 74. WAIT Line Sampling in Variable-Cycle Timing . . . . . . 167 Figure 75. Interrupt Acknowledge . . . . . . . . . . . ...

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Parallel Input/Output (continued) Figure 98. Example of I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . .201 Figure 99. Control Mode Application ...

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Z80 CPU Peripherals User Manual xiv Serial Input/Output (continued) Figure 124. Read Register 2 (Channel B Only 301 Figure 125. Synchronous/Asynchronous Processor-to-Processor Commu- ...

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List of Tables Counter/Timer Channels Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Direct Memory Access Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. ...

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Z80 CPU Peripherals User Manual xvi Parallel Input/Output Table 19. Serial Input/Output Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. ...

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Serial Input/Output (continued) Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. List of Tables Sync Modes . . . . . . . . ...

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Z80 CPU Peripherals User Manual xviii UM008101-0601 List of Tables ...

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Counter/Timer Channels CTC FEATURES • Four independently programmable counter/timer channels (CTC), each with a readable down-counter and a selectable 16 or 256 prescaler. Down-counters are reloaded automatically at zero count • Selectable positive or negative trigger initiates timer operation • ...

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microcomputer system requirements for event counting, interrupt and interval timing, and general ...

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The CPU bus interface logic allows the CTC device to interface directly to the CPU with no other external logic. However, port address decoders and/or line buffers may be required for large systems. A block diagram of the Z80 ...

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Channel Control Register and Logic The Channel Control register (8-bit) and ...

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Table 2. Channel Control Register Interrupt Mode Prescaler Value* R/W R/W R/W Bit Number Field 7 Interrupt 6 Mode 5 Prescaler Value* 4 CLK/TRG Edge Section 3 Time Trigger* 2 Time Constant 1 Reset 0 Control or ...

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the down-counter counts to zero, the down-counter is automatically reloaded with the ...

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Interrupt Control Logic The Interrupt Control Logic insures that the CTC acts in accordance with Z80 system interrupt protocol for Nested Priority Interrupting and Return From Interrupt. The priority of any system device is determined by its physical location in ...

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CTC channel may be programmed to request an interrupt every time ...

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According to Z80 system convention, all addresses in the interrupt service routine table place their low-order byte in an even location in memory, and their high-order byte in the next highest location in memory. This location is always odd so ...

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CPU Data Bus CTC Control from CPU Daisy-Chain Interrupt Control Figure 4. D4 ...

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GND N ZC/TO0 N/C 11 ZC/TO1 12 ZC/TO2 13 14 IORQ N/C 15 IEO 16 N/C 17 Figure 6. UM008101-0601 Z80 CTC 18 19 ...

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N/C CS1 CLK/TRG3 CLK/TRG2 N/C N/C CLK/TRG1 CLK/TRG0 N/C +5V N/C Figure 7. ...

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Table 4. Channel Select Truth Table Channel 0 Channel l Channel 2 Channel 3 CE Chip Enable (input, active Low). A Low level on this pin enables the CTC to accept control words, interrupt vectors, or time constant data words ...

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IORQ Input/Output Request from CPU (input, active Low). The IORQ signal is used ...

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CTC channel. Therefore, this signal blocks lower- priority devices from interrupting while a higher-priority interrupting device is being serviced by the CPU. INT Interrupt Request (output, open-drain, active Low). This signal goes true when a CTC ...

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CTC OPERATING MODES Overview At power-on, the Z80 CTC state is undefined. Asserting ...

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Additionally, if the channel is pre-programmed by bit 7 of the channel control word, an interrupt request sequence is generated. For more details, see the CTC Interrupt Servicing section The ...

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Timing may be initialized automatically or with a triggering edge at the channel’s ...

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Loading The Channel Control Register To load a Channel Control Word, the CPU performs a normal I/O Write sequence to the port address corresponding ...

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Bit Number Field 4 CLK/TRG Edge Section 3 Time Trigger* 2 Time Constant ...

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System clock the prescaler factor 256, c and TC is the time constant data word. Bit Defined for Timer mode only. Prescaler factor is 256. Bit ...

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Loading The Time Constant Register A Time Constant Data Word is written to ...

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Service Interrupt Routine Starting Address Figure 8. Table 7. Interrupt Vector Register Supplied by User R/W Bit Number Field 7–3 Reserved 2–1 Channel Identifier 0 Word UM008101-0601 Desired starting address pointed to by: Low Order Contents High ...

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CTC TIMING Overview This section describes the timing relationships of the relevant CTC ...

Page 43

CS0. CS1, CE IORQ RD M1 Figure 9. CTC Read Cycle Figure 10 illustrates the timing associated with the CTC Read cycle. This sequence is used when CPU reads the current contents of the down counter. During clock cycle T2, ...

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CLK CS0. CS1, CE IORQ RD M1 DATA Figure 10. CTC Counting and ...

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The timing function is initiated in synchronization with Φ. A minimum setup time is required between the active edge of the CLK/TRG and the rising edge of Φ. If the CLK/TRG edge ...

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The CTC’s interrupt control logic ensures that it acts in accordance with Z80 ...

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CLK M1 IORQ RD IEI INT DATA Figure 12. Return from Interrupt Cycle Figure 13 illustrates the timing associated with the RETI Instruction. This instruction is used at the end of an Interrupt Service Routine to initialize the daisy-chain enable ...

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CLK – IEI IEO INT *INT goes Low ...

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Highest Priority Channel Channel IEI 1. Priority interrupt daisy chain before any interrupt occurs IEI 2. Channel 2 requests an interrupt and is acknowledged IEI 3. Channel 1 interrupts, suspends servicing of Channel ...

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UM008101-0601 Counter/Timer Channels ...

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Direct Memory Access DMA OVERVIEW Direct Memory Access (DMA) and DMA Controllers are dedicated to controlling high-speed block transfers of data independently of the CPU. DMA data transfers are usually between memory and I/O, or vice versa. A DMA controller ...

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Figure 15. The Z80 and Z8000 CPUs both have block-transfer and string-search ...

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The I/O device interrupts the CPU and the block transfer instruction is executed in the CPU interrupt service routine. This method has a response time of at least µs, even in 4 MHz Z80A and Z8000 ...

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DMACs are used when one or more of the following situations or require- ...

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DMA Characteristics All DMACs are programmable because the CPU must at least write a block length (byte count) and starting memory address to a DMAC before they can begin managing a data transfer. The starting address is incre- mented or ...

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Transfer Methods Figure 16 compares conventional CPU instructions and the Z80 and Z8000 ...

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Additionally, it reduces DMA throughput. All DMA transfers interrupt dynamic memory refresh by the CPU and most of them idle the CPU. It is, therefore, important to consider these implications when making ...

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Modes of Operation Within each of the methods illustrated in Figure 16c and ...

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Bus Control Most DMACs do not control the system bus in the same way that a CPU controls it. For example, many DMACs do not have a straightforward interface to the system data bus but rather multiplex a portion of ...

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For example, the Z80 DMA can be programmed either to stop, interrupt the ...

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DMA FUNCTIONAL DESCRIPTION Features • Single Highly Versatile Channel • Dual Port Address Generation with Incrementing, Decrementing, or Fixed Address in Both Ports • Buffered Address and Block-Length Registers • 64 Kbyte Maximum Block Length • 2 MHz ...

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• Programmable Force Ready Condition • Programmable Active State for Ready Line • ...

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If multiple channels are needed, multiple Z80 DMAs can be easily inte- grated. The interrupt structure is fast and versatile. Interrupt signals and vectors can be generated under several ...

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Classes of Operation The Z80 DMA has three basic classes of operation, and ...

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Sequential Transfer (Flow through) CPU MEMORY Simultaneous Transfer (Flyby) CPU MEMORY Search Only CPU MEMORY Sequential ransfer/Search CPU MEMORY Simultaneous ransfer/Search CPU MEMORY Figure 18. Class of Operation < %27 2GTKRJGTCNU Read Write DMA I/O Read/Write DMA I/O Read DMA ...

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< %27 2GTKRJGTCNU 7UGT /CPWCN  ...

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Transfer Memory-to-I/O (optional search) 2. Transfer I/O-to-Memory (optional search) 3. Transfer Memory-to-Memory (optional search) 4. Transfer I/O-to-I/O (optional search) 5. Search Memory 6. Search I/O Figure 19. Modes of Operation Within any class of operation, the Z80 DMA can ...

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port’s Ready line goes inactive before this occurs, the DMA pauses until the ...

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Increment/Decrement Source-Port Address Read Source-Port Data Increment/Decrement Destination Port Address Write Data to Destination Port Byte Match Increment Byte Counter Figure 20. UM008101-0601 YES ? NO Set Status Flag • Continue • Release Bus • Interrupt Transfer/Search One Byte < ...

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Release Bus (CPU Executes at least one Machine Cycle) Figure 21. UM008101-0601 Enable ...

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Request Bus NO RDY Active ? Figure 22. In the Burst mode (Figure 22), the bus is requested in the same manner as previously, but when the DMA has control of the bus it continues to transfer bytes until it ...

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attains the bus, the transfers are made at maximum speed. If the transfers ...

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RDY Active Figure 23. UM008101-0601 Enable DMA RDY Active ? YES Request Bus NO Transfer/Search One Byte YES Figure 20) (See ? End NO of Block ? YES Set Status Flag • Interrupt • Release Bus • Auto Restart Continuous ...

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Transfer Speed The Z80 DMA has one of the fastest maximum transfer rates ...

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Table 8. Maximum Transfer and Search Speeds (Burst and Continuous Modes) Action DMA Simultaneous Transfer DMA Search Only DMA Simultaneous Transfer/Search DMA Sequential Transfer DMA Sequential Transfer/Search CPU Block Transfer Instruction Table 9. Reduction in Z80 CPU Throughput per Kbaud ...

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Variable addresses can either increment or decrement automatically from the programmed starting address. ...

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The match byte written into the DMA is masked with another byte so that only certain bits within the match byte can be compared with the corre- sponding bits in the data bytes being searched. Interrupts The DMA can be ...

Page 78

Auto Restart Block transfers can be repeated automatically by the DMA. This function ...

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Wait cycles are used), thereby increasing or decreasing the speed at which all DMA signals change. Second, the four signals in each port (I/O Request, Memory Request, ...

Page 80

Table 10. Events and Actions Event End-of-Block Byte Match (Compare) Pulse-control byte matches ...

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BAI Bus Acknowledge In (input, active Low). Signals that the system buses have been released for DMA control. BAO Bus Acknowledge Out (output, active Low). In multiple-DMA configura- tions, this pin signals that the CPU has relinquished control of the ...

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states to be inserted in the DMA’s operation cycles, thereby slowing the DMA ...

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INT/PULSE Interrupt Request (output, active Low, open-drain). This requests a CPU interrupt when brought Low while the DMA is not the bus master. The CPU ...

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when M1 occurs without an active RD or IORQ for at least two ...

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DMA-controlled write to a memory or I/O port address. RESET Reset (input, active Low) is available in the CMOS PLCC version only. A Low in this signal resets the DMA. System Data Bus BUS Control ...

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...

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 #  % . -  & ...

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...

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Interrupt and Bus Priority Logic System Data Bus (8-Bit) Bus Control Control Logic Figure 29. Z80 DMA Block Diagram < %27 2GTKRJGTCNU Pulse BYTE Logic Counter Port A Address Internal Bus Control Port B BYTE and Address Match Status Logic ...

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< %27 2GTKRJGTCNU 7UGT /CPWCN  ...

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DMA while the CPU has the bus between byte transfers. This allows the next block, which can be an Auto Restart block, to begin quickly at a new location. Notice that the ...

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WRQ Base Register Byte Port A Starting Address Register ...

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Address and Byte Counting Addresses for either port may be fixed at their programmed starting address, or they may be incremented or decremented from the programmed starting address by the address counters. The block length programmed into the DMA is ...

Page 94

Table 11. Contents of Counters After DMA Stops Because of End-of-Block (Transfer Operations) ...

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Table 12. Contents of Counters After DMA Stops Due to Byte Match (Search or Transfer/ Search Operations) Match Occurs Class Mode On This Byte Continuous M : Notes * Address can increment (+) or decrement (-) from the programmed starting ...

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When the DMA has requested and received the bus from the CPU, other ...

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Bus Request Daisy-Chains Multiple DMAs can be linked in a prioritized daisy-chain for the purpose of requesting the bus. Figure 31 illustrates this procedure. Each DMA’s BUSREQ pin is bidirectional output, it requests the bus input, ...

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Interrupts Conditions and Methods The Z80 CPU prioritizes external events in the following ...

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Auto Restart. Therefore, the interrupt vector cannot indicate the specific interrupt cause, for example, Status Affects Vector is not effective. The Z80 CPU acknowledges the interrupt by pulling its ...

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End-of-Block or Byte Match DMA Releases Interrupts CPU CPU Acknowledges DMA Passes Interrupt ...

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CPU to a temporary register. It normally identifies the interrupting device and it can also identify the cause of the interrupt (actually the current state of certain status bits). The I Register of the Z80 CPU (when the CPU is ...

Page 102

MEMORY A. B. Service Routine C. Service Routine Figure 33. Interrupt Latches Two ...

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Prevents interrupts from lower priority devices in an interrupt daisy-chain – Prevents further bus requests by this DMA If the Interrupt on RDY (interrupt before requesting bus) option is selected, the IP latch is set when the Ready line ...

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Interrupt On Ready Normally, when the DMA has been enabled by the CPU ...

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Reset and disable DMA interrupts – Enable DMA interrupts – Disable DMA interrupts • Load new starting addresses and block length – Continue prior address counting – Clear block length counter • Force the Ready condition • Read the ...

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• Resets the Interrupt Under Service (IUS) latch in the DMA, thereby allowing ...

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Bus-requesting daisy-chains do not have this preemption or nesting ability. Instead, any peripheral that is able to get the bus keeps it ...

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Figure 38. PROGRAMMING Overview The DMA must be programmed before use. Its control ...

Page 109

It is not possible for the DMA to program itself by directing transfers of control bytes from memory to its own internal registers. When DMA interrupt vectors are used in a Z80 environment, the Z80 CPU should be programmed ...

Page 110

Write Registers Control bytes must be written to all relevant registers in the ...

Page 111

Pointer Bits Figure 39. Write Register 0 Group The WR0 base register byte is identified bit 7 and any combi- nation except bits 0 and ...

Page 112

Source and Destination Bit 2 indicates the source port and, by implication, the ...

Page 113

Figure 40. Block Length All operations must have a declared block length because the default values at power-up are unpredictable for block length. These registers are written to by setting pointer bits ...

Page 114

Write Register 1 Group Bits and 0, as Figure 41 ...

Page 115

In addition, bits and 2 of the variable-timing byte allow termination of various lines 1/2 cycle earlier than specified in bits 1 and 0. The chapter on “Timing” illustrates and describes the effect of this in detail. ...

Page 116

Write Register 2 Group Bits and 0, depicted in Figure ...

Page 117

Stop on Match Setting bit 2 of the base register byte to 1 causes the DMA to stop and release the bus when a data byte matches the match byte, which is described later. A search or transfer/search operation must ...

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DMA Enable A1 in bit 6 of the base register enables the DMA ...

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Starting Address (Port B) The starting address for Port B in the next two bytes may be specified by setting bits 2 and 3 of the base register to 1. This is only needed if Port B is used, and ...

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Interrupt Vector Bit 4 of the interrupt control byte allows the interrupt vector ...

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Byte = Continuous = Burst = Do Not Program = Interrupt on RDY = 1 Status Affects Vector = 1 Vector is automatically Modified as shown only if Status Affects Vector bit is set Figure 44. Write Register 5 Group ...

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End-of-Block Action Bit 5 specifies either a stop (bus release auto ...

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Only 1 = CE/WAIT Only 0 = Stop on End-of-Block 1 = Auto Restart on End-of-Block Figure 45. Write Register 6 Group The base register byte for ...

Page 124

• Reinitialize Ports A and B to standard Z80 cycle timing (see WR1 ...

Page 125

This special situation is discussed in a later section entitled “Fixed-Address Destination Ports.” If the DMA inactive state (Table 15) when the LOAD command is written, another DMA control byte must ...

Page 126

the routine is being executed. Near the end of the routine, the CPU ...

Page 127

Enable Interrupts (AB) See the preceding description of DISABLE INTERRUPTS. A Z80 CPU environment uses this command at power-up to enable the interrupt logic at the beginning (the DMA comes up with this logic disabled not needed, however, ...

Page 128

end of the service routine, the CPU writes a RESET AND DISABLE INTERRUPTS ...

Page 129

RETI instruction Read Status Byte (BF) This command causes the next CPU read of the DMA to access the status byte, which is illustrated in “Read Registers” on page 114. If other read registers ...

Page 130

the DMA, reinitialization of the status bits may remove the condition that stopped ...

Page 131

Initiate Read Sequence (A7) This command initiates the read-sequence pointer command, allowing the next CPU read instruction to the DMA access to the first (low-order) read register designated as readable by the read mask. When started, the read sequence specified ...

Page 132

Enable DMA (87) This command allows the DMA to request the system bus ...

Page 133

Read Status Byte This command causes the next CPU read of the DMA to access the status byte, which is the first read register. Initiate Read Sequence This command initializes access to a repeatable series of reads that follow the ...

Page 134

Bit 0 Indicates whether the DMA has requested the bus after the fast ...

Page 135

Read Register 1 Read Register 2 Read Register 3 Read Register 4 Read Register 5 Read Register 6 Figure 47. Byte Counter (RR1, RR2) This 16-bit counter is cleared to ...

Page 136

Table 11 and Table 12 illustrate how the pipelining of data affects the ...

Page 137

Table 15 lists the order in which control bytes must be written for the initialization ...

Page 138

Table 15. Control Byte Order (Continued) Initialization/Reinitialization Sequence REINITIALIZE STATUS BYTE Command READ ...

Page 139

Address Loading Write starting addresses to the starting-address registers for each port using WR0 (Port A) and WR4 (Port B). They are loaded to the address counters by the LOAD command. The addresses must he written to the registers before ...

Page 140

• • • 7. Enable DMA with the Interrupts The interrupt vector (WR4) ...

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ENABLE AFTER RETI 6. ENABLE DMA • • • 7. RETI Interrupts at end-of-block, for example, might occur when reading a floppy disk. If the disk transfers 128-byte records, the DMA can be made to interrupt at the end ...

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processed until the bus is released). Second, to enable the DMA, the ENABLE ...

Page 143

End-of-Block After a stop or stop and interrupt on end-of-block (WR4 or WR5), where it is necessary to perform additional operations with the DMA, write the same sequence of commands listed immediately under “Byte Matching (Searches)” on page 124. Table ...

Page 144

Variable Timing The timing on the RD, WR, MREQ, and IORQ lines can ...

Page 145

SEQUENCE Table 16 illustrates a program to transfer data from memory (Port peripheral device (Port B). In this example, the Port A memory starting address is number of data bytes to be transferred ...

Page 146

Table 16. Sample DMA Program (Continued) D7 WR4 sets mode to 1 Burst ...

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Note: The actual number of bytes transferred is one more than specified by the block length. * These entries are necessary only in the case of a fixed destination address. Z80 DMA and CPU As a member of the Z80 ...

Page 148

up. A complementary-transistor driver for Z80/Z8000 systems is depicted in Figure 48. Chip ...

Page 149

Figure 49c depicts a one-of-eight TTL decoder which provides chip enable signals for eight different peripheral devices. Address bits A0 and A1 are often used directly by peripherals such as the Z80 SIO, PIO, and CTC, and so are not ...

Page 150

DMA responds to I/O addresses 00H through 77H B PROM determines DMA ...

Page 151

CPU has relinquished the bus. Therefore, if this DMA is bus master, it samples the WAIT signal for these requests. A simple 2-input multiplexer steers the CE/WAIT signals as depicted in Figure 50. Using BUSACK assumes that there is only ...

Page 152

WAIT (From Peripheral or Memory Logic) CE (From Decoder) BUSACK Figure 50. BUSACK ...

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DMA IORQ MEMORY Figure 52. UM008101-0601 WR BUSACK HIGH SEL MRD MWR Address and Data Buses Simultaneous Transfer < ...

Page 154

MWR CLK BUSACK Figure 53. Bus Buffering Microcomputer systems using DMA often include ...

Page 155

CPU and DMA address pins. For example system with one CPU and one DMA, the BUSACK signal can disable CPU buffers and enable DMA buffers when it is active. Where there ...

Page 156

signals. To maximize current, the system’s BUSREQ pull-up resistor can be as low ...

Page 157

DMA.CE SIO.CE PIO.CE CTC.CE RD DMA.HAS.BUS IORQ M1 CARD.IEO CARD.IEI Figure 54. Z80 DMA and Z80 SIO Example A common DMA application is performing data transfers over a serial data link. The Z80 SIO peripheral is used to interface to ...

Page 158

The event sequences for SIO-DMA transfers are described in Table 17 and Table ...

Page 159

Table 18. Transmit Event Sequence (Continued) Event DMA I/O write cycle begins DMA terminates BUSREQ DMA I/O write cycle ends CPU terminates BUSACK and regains control of bus In an interrupt-driven CPU transfer scheme, the SIO must interrupt the CPU ...

Page 160

represent the fractional reductions in CPU throughput per Kbaud trans- ferred. DMA sequential ...

Page 161

ZC/TO1 ZC/TO2 RxCA TxCA RxCB TxCB Figure 55. Using The Z80 DMA With Other Processors The Z80 DMA offers great versatility and is a powerful alternative for board designers. Because the DMA is designed as a member of the Z80 ...

Page 162

the Z80 bus, to function. These functions are described in the following sections, ...

Page 163

Bus Characteristics Similar to the Z80, the 8080 and 8085 have 8-bit data paths and 16-bit addresses. The DMA is matched well to these numbers; it can search whole data words and directly address any byte in the memory. The ...

Page 164

Multiplexed Address and Data Bus Figure 56. Many processors encode their control signals, ...

Page 165

Non-Z80 interrupt environments do not use the IEI and IEO signals, and often they use separate interrupt controllers to generate vectors, and handle acknowledgement and return in different ways, or not at all. Interrupt request is usually easy: active levels ...

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LA4 LA3 DS AS LA5 +5V From Z8000 Data Bus PRE D IORQ ...

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PERFORMANCE LIMITATIONS Bus Contention Using the Direct Memory Access (DMA) as bus master can negatively effect CPU activity by preventing the CPU from fetching and executing instructions. This method of bringing the CPU to a halt creates problems, including: • ...

Page 168

Continuous Mode Continuous Mode monopolizes the bus until the end-of-block or byte match ...

Page 169

System throughput is decreased for applications requiring frequent DMA reprogramming or extensive interrupt service of data-independent DMA functions more efficient to transfer large blocks of repetitive data. TIMING The CPU As Bus Master When the CPU is the ...

Page 170

IORQ D7–D0 Figure 59. To write to the DMA control bites, the following ...

Page 171

IORQ D7–D0 Figure 60. The DMA As Bus Master Sequential Transfers In sequential transfer and transfer/search operations, which both have the same timing, data is latched onto the bus by the rising edge of the RD sig- nal, with standard ...

Page 172

Simultaneous Transfers The timing for simultaneous transfers and simultaneous transfer/searches is the same. ...

Page 173

CLK A15–A0 MREQ READ RD IORQ WRITE WR D7–D0 CE/WAIT Figure 61.Sequential Memory-to-I/O Transfer, Standard Timing (Searching is Optional) UM008101-0601 Memory Read Memory Drive DMA < ...

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CLK A15–A0 IORQ READ RD IORQ MREQ WRITE WR CE/WAIT Figure 62. UM008101-0601 ...

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Cycle CLK A15–A0 MEMRD D7–D0 IOWR CE/WAIT Figure 63. Mode) UM008101-0601 Cycle Simultaneous Memory-to-I/O Transfer (Burst and Continuous < ...

Page 176

Cycle 1 CLK A15–A0 MEMRD D7–D0 IOWR CE/WAIT DMA Drives the Last Data ...

Page 177

BUSREQ and BAI lines, which is explained later. Search-Only The standard timing for search-only operations is identical to the read cycles of Figure 61 and Figure 62. Search-only is equivalent to read-only. ...

Page 178

CLK Active RDY Inactive BUSREQ BAI Note: RDY is detected as a level, ...

Page 179

CLK BUSREQ BAI Figure 66. The next bus request for the next byte comes after both BUSREQ and BAI have returned High Z80 environment, BAI returns High one clock cycle after BUSREQ returns High. Bus Release on End-of-Block. ...

Page 180

Bus Release on Match When the DMA is programmed to stop (release the ...

Page 181

The action on BUSREQ is thus somewhat delayed from action on the RDY line. The DMA always completes the current byte oper- ation in an orderly fashion before releasing the bus. CLK Active RDY Inactive BUSREQ Figure ...

Page 182

Active RDY BUSREQ BAI A15–A0 MREQ RD D7–D0 Figure 70. UM008101-0601 RDY Line ...

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RDY BUSREQ BAI A15–A0 MREQ RD D7–D0 Figure 71. UM008101-0601 RDY Line in Burst Mode < ...

Page 184

RDY BUSREQ BAI A15–A0 MREQ RD D7–D0 Figure 72. Variable Cycle and Edge ...

Page 185

CLK A15–A0 IORQ MREQ RD, WR Figure 73. In the Variable-Cycle mode, unlike default tuning, IORQ comes active one- half cycle before MREQ, RD, and WR. CE/WAIT can be used to extend only the clock cycle variable ...

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and any functions created from it by external logic in simultaneous transfer operations ...

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Interrupt on RDY (interrupt before requesting the bus) does not directly affect the BUSREQ line. Instead, the interrupt service routine may handle this by issuing the following commands to WR6: • Enable after Return From Interrupt (RETI) Command — B7H ...

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Last M Cycle of Instruction Last T State CLOCK INT A7–A0 M1 MREQ ...

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REGISTER BIT FUNCTIONS Write Register Bit Functions Figure 76. WR Ends 1/2 Cycle Early = 0 RD Ends 1/2 Cycle Early = 0 MREQ Ends 1/2 Cycle Early = 0 Figure 77. ...

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Ends 1/2 Cycle Early = 0 RD Ends 1/2 Cycle Early = ...

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Continuous = Burst = Do Not Program = Interrupt on RDY = 1 Status Affects Vector = 1 Vector is Automatically ‘Status Affects Vector’ Figure 80. UM008101-0601 Base Register ...

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...

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Read Register Bit Functions Read Register 1 Read Register 2 Read Register 3 Read Register 4 Read Register 5 Read Register 6 Figure 83. UM008101-0601 Status Byte 1 = DMA ...

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UM008101-0601 Direct Memory Access ...

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Parallel Input/Output OVERVIEW The Z80 Parallel Input/Output (PIO) Circuit is a programmable, two-port device that provides a TTL-compatible interface between peripheral devices and the Z80 CPU. The CPU configures the Z80 PIO to interface with a wide range of peripheral ...

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• Four modes of port operation with interrupt-controlled handshake: – Byte Output – ...

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The 2-bit mode control register is loaded by the CPU to select the desired operating mode (byte output, byte input, byte bidirectional bus, or bit control mode). All data transfer between the peripheral device and the CPU is achieved through ...

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Mode Control Reg (2 Bits) Internal Bus Mask Mask Control Reg (8 Bits) ...

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The interrupt control logic section handles all CPU interrupt protocol for nested priority interrupt structures. The priority of any device is determined by its physical location in a daisy-chain configuration. Two lines are provided in each PIO to form this ...

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PIN DESCRIPTION Figure 3 illustrates a diagram of the Z80 PIO pin configuration. ...

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