Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 45
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
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22
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CTC INTERRUPT SERVICING
UM008101-0601
Overview
detected asynchronously and must have a minimum width. The timing
function is initiated in synchronization with Φ. A minimum setup time is
required between the active edge of the CLK/TRG and the rising edge of Φ.
If the CLK/TRG edge occurs closer than this, the initiation of the timer
function will be delayed one cycle of Φ.
Figure 11.
Each CTC channel may be individually programmed to request an
interrupt every time its down-counter reaches zero. The purpose of a CTC-
generated interrupt is to force the CPU to execute an interrupt service
routine. To use this feature the Z80 CPU must be programmed for Mode 2
interrupt response. In this mode, when a CTC channel interrupt request is
acknowledged, a 16-bit pointer must be formed to obtain a corresponding
interrupt service routine. The lower eight bits of the pointer are provided
by the CTC in the form of an interrupt vector unique to the requesting
channel. For further details, refer to the Z80 CPU User’s Manual.
CLK/TRG
Internal
Counter
ZC/TO
CTC Counting and Timing
Lead
Time
Zero
Count
Counter/Timer Channels
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
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