Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 230

• Manufacturer Part Number: Z0847006PSG
• Description: IC 6MHZ Z80 NMOS DART 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z0847006PSG

• Processor Type: Z80
• Features: Dual Channel Asynchronous Receiver/Transmitter (DART)
• Speed: 6MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Mounting Style: Through Hole
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 847006
• Rohs Compliant: Yes
• Clock Frequency: 6MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

210
PIN DESCRIPTION
UM008101-0601
<   % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Pin Functions
D7-D0 System Data Bus (bidirectional, tristate). The system data bus
transfers data and commands between the CPU and the Z80 SIO. D0 is
the least-significant bit.
B/A Channel A or B Select (input, High selects Channel B). This input
defines which channel is accessed during a data transfer between the CPU
and the Z80 SIO. Address bit A0 from the CPU is often used for the selec-
tion function.
C/D Control Or Data Select (input, High selects Control). This input
defines the type of information transfer performed between the CPU and
the Z80 SIO. A High at this input during a CPU write to the Z80 SIO
causes the information on the data bus to be interpreted as a command for
the channel selected by B/A. A Low at C/D indicates that the information
on the data bus is data. Address bit A1 is often used for this function.
CE Chip Enable (input, active Low). A Low level at this input enables the
Z80 SIO to accept command or data inputs from the CPU during a write
cycle, or to transmit data to the CPU during a read cycle.
Φ System Clock (input). The Z80 SIO uses the standard Z80A System
Clock to synchronize internal signals. This is a single-phase clock.
M1 Machine Cycle One (input from Z80 CPU, active Low). When M1 is
active and RD is also active, the Z80 CPU is fetching an instruction from
memory; when M1 is active while IORQ is active, the Z80 SIO accepts
M1 and IORQ as an interrupt acknowledge if the Z80 SIO is the highest
priority device that has interrupted the Z80 CPU.
IORQ input/Output Request (input from CPU, active Low). IORQ is used
in conjunction with B/A, C/D, CE, and RD to transfer commands and data
between the CPU and the Z80 SIO. When CE, RD, and IORQ are all active,
the channel selected by B/A transfers data to the CPU (a read operation).
Serial Input/Output