SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 58

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

7.5
In addition to acting as general-purpose registers, registers R8-R14 can also serve as pointer registers. Instructions can access
RAM locations by referring to any of these registers. In normal operation, register R15 is reserved for use as a stack pointer.
7.6
Registers R0..R15 are mapped into RAM via the REGBANK register. The REGBANK register is loaded with a base address, of
which the 11 most significant bits are used. A read from or write to one of the registers will generate a RAM address by:
For example, if the REGBANK register is left at its default value of 100 hex, a read of register R14 would read address 11C hex.
Note:
Regardless of the value loaded into the REGBANK register, bits 0..4 will be ignored.
7.7
The SL11R Processor uses these flags:
Note:
Flag behavior for each instruction will be described in the following section
7.8
To understand addressing modes supported by the SL11R Processor, you must know how the instruction format is defined. In
general, the instructions include four bits for the instruction opcode, six bits for the source operand, and six bits for the destination
operand.
Some instructions, especially single operand-operator and program control instructions, will not adhere strictly to this format. They
will be discussed in detail in turn.
Document #: 38-08006 Rev. **
Register
REGBANK
R14
RAM Location
FLAG
bit:
ADD
bit:
• Shifting the 4 least significant bits of the register number left by 1.
• OR-ing the shifted bits of the register number with the upper 11 bits of the REGBANK register.
• Forcing the Least Significant Bit to 0.
Z
C
O
S
I
General Purpose/Address Registers
REGBANK Register (0xC002: R/W)
Flags Register (0xC000: Read Only)
Instruction Format
15
15
0
14
14
opcode
0
Hex Value
0100
000E << 1 = 001C
011C
Zero: instruction execution resulted in a result of 0
Carry/Borrow: Arithmetic instruction resulted in a carry (for addition) or a borrow (for subtraction)
Overflow: Arithmetic result was either larger than the destination operand size (for addition) or smaller
than the destination operand should allow for subtraction
Sign: Set if MS result bit is “1”
Global Interrupts Enabled if “1”
13
13
0
12
12
0
11
11
0
10
10
Binary Value
0 0 0 0 0 0 0 1 0 0 0 x x x x x
x x x x x x x x x x 0 1 1 1 0 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0
0
9
source
9
0
8
8
0
7
7
0
6
6
0
5
5
0
4
4
I
destination
3
S
3
2
O
2
1
C
1
0
0
Z
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SL11R