SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 37

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

4.17.10 PWM Channel 3 Stop Register (0xC0F8: R/W)
4.17.11 PWM Cycle Count Register (0xC0FA: R/W)
Note: Number of OS Cycles to run = C+1. Example for 1 Cycle, set C=2
4.18
This mode is currently used by the DVC 8-Bit DMA and 8/16-Bit DMA modes. In DVC 8-Bit DMA mode, the DMA data path will
be 8, which corresponds to SD7-SD0. In the 8/16-Bit DMA mode, the DMA data path can be configured as either 8 or 16.
4.18.1
External device data presented to S15-SD0/SD7-SD0 is automatically written into the RAM of the SL11R, under fast DMA control.
The DMA must be enabled in the DMA Control and Address register.
4.18.2
Document #: 38-08006 Rev. **
D15-10
D9-0
D15-0
D2
D1
D0
Note for DVC 8-Bit DMA mode:
D15-0
Fast DMA Mode
DMA Control Register (0xC02A: R/W)
Low DMA Start Address Register (0xC02C: R/W)
This register contains the low order word of the starting DMA address.
D15
A15
D15
D15
C15
0
D14
A14
D14
D14
C14
0
Reserved
S9-S0
C15-0
TSZ
DIR
DMA
Set Transfer Size to 16 bits for the DVC 8-Bit DMA mode.
Set DMA Direction for Peripheral to Memory for DVC 8-Bit DMA mode.
A15-A0
D13
D13
D13
C13
A13
0
D12
A12
D12
D12
C12
0
D7
0
always ’0’ ’s.
Stop Count for PWM Channel 3.
Number of cycles to run in one-shot mode (0-64K)
The OS bit in the PWM Control Register must be set.
Transfer Size. 8 bit when set to ’1’, 16-bit when set to ’0’
DMA Direction. When set to ’0’, data transfers from Peripheral to Memory. When set to
'1’ Memory to Peripheral.
DMA Enabled when set to '1'. Bit clears to ‘0’ when DMA is done.
Low 16 Bits of DMA address
D11
A11
D11
D11
C11
0
D6
0
D10
A10
D10
D10
C10
D5
0
0
D4
D9
D9
C9
D9
A9
S9
0
D3
D8
S8
D8
C8
D8
A8
0
TSZ
D7
S7
D7
C7
D7
A7
D2
D6
D6
C6
S6
D6
A6
DIR
D1
D5
D5
C5
S5
D5
A5
DMA
D0
D4
S4
D4
C4
D4
A4
D3
S3
D3
C3
D3
A3
D2
S2
D2
C2
D2
A2
D1
D1
C1
S1
D1
A1
D0
D0
C0
S0
D0
A0
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SL11R