SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 15

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

3.20.1
In the GPIO mode, the SL11R has up to 32 General-Purpose IO signals available. However, four pins that are used by the UART
and the 2-wire serial interface that cannot be used as GPIO pins. A typical application for this GPIO is the Parallel Port to USB.
The SL11R executes at 48MHz, which is fast enough to generate any Parallel Port timing. The SL11R also includes a special
mode for EPP timing designed for special devices that have no delay in EPP mode. On any other available General Purpose
programmable I/O, the pins can be programmed for peripheral control and/or status.
Note: The Fast DMA and PWM Interfaces are not supported in this mode.
3.20.2
This Mode includes the Mailbox Protocol and DMA Protocol. The Mailbox Protocol allows asynchronous exchange of data
between the external Processor (i.e. DSP or other Microprocessor) and SL11R via SD0-SD15 (GPIO 0-15) which is a bidirectional
data port. The DMA Protocol allows large blocks of data to be transferred to or from the SL11R via the 8/16-bit DMA port.
3.20.3
This mode is designed to interface with a special optimized high-speed EPP interface. In this mode, the SL11R processor has
direct access to the EPP control port.
Note: The Fast DMA and PWM Interface are not supported in this mode.
3.20.4
This DVC 8-bit DMA mode is designed to interface with CCD cameras. Camera control and setup is performed through the serial
control bus. The SL11R 16-bit processor has direct access to the control port and the camera operation is dependent on com-
mands passed from the USB Host to the SL11R. Raw video data from the CCD Camera is input to the SL11R on the 8-bit video
data bus (SD7-SD0) using a combination of clock, control signals and 8-bit DMA.
Note: The PWM Interface is not supported in this mode.
4.0
4.1
The SL11R has a built-in 3Kx16 internal masked ROM that contains software bootstrap code to allow programs in an external
8/16-bit ROM to be executed. The ROM code can also load data from the 2-wire serial interface into internal RAM for execution.
In addition, the internal BIOS ROM contains the Interrupt Service Routines (see [Ref. 1] SL11R_BIOS for information) that support
the USB, 2-wire serial interface, UART interfaces and Boot-Up options (Boot-up from 2-wire serial interface or External ROM).
This SL11R BIOS ROM eases software development of all SL11R interfaces. The SL11R Chip is ready for all the USB enumer-
ation and download/program code.
The SL11R Internal Masked ROM (i.e. SL11R BIOS) is mapped from address 0xE800 to 0xFFFF. On power up or hardware reset,
the SL11R processor jumps to the address of 0xFFF0, which contains a long jump to the beginning of the internal ROM of address
0xE800. See Table 4-1.
Table 4-1. Internal Masked ROM (SL11R BIOS)
4.2
The SL11R BIOS ROM reserves addresses from 0xC100 to 0xE800 for external ROM. During BIOS initialization, the SL11R will
scan for the signature ID (0xCB36) at location 0xC100. After a valid signature is detected, execution will begin at address 0xC102
(see [Ref. 1] SL11R_BIOS for more information). The signal nXROMSEL is used to enable the external ROM. It is mapped from
Document #: 38-08006 Rev. **
0xE800-0xFFEF
0xFFF0-0xFFF3
0xFFF4-0xFFF9
0xFFFA-0xFFFB
0xFFFC-0xFFFD
0xFFFE-0xFFFE
0xFFFF-0xFFFF
Address
General Purpose IO mode (GPIO)
8/16-bit DMA Mode
Fast EPP Mode
DVC 8-bit DMA Mode
Internal Masked ROM: 0xE800-0xFFFF
External ROM: 0xC100-0xE800
Interface
SL11R BIOS code/data space
Jump to 0xE800
Reserved for future use.
ROM BIOS Checksum
SL11R BIOS Revision
Peripheral Revision
QT Engine Instruction Revision
Memory Description
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SL11R