SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 45

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

5.3.7.4 Serial Interface Data Read Register
Notes:
The clock rate for the serial operation is 12MHz base on the processor clock at 48MHz. To change the clock rate user can change
the processor clock rate via the register C008H.
A delay is needed between back to back serial accesses to allow serial shifting to occur.
GPIO11 will be used as the DATAS.
GPIO26 will be used as the CLKS.
GPIO25 will be used as the nENS (Can use this as the interrupt IRQ1).
The register C006H need to select this mode to make the interface work.
5.4
This mode is designed to interface with CCD cameras. Camera control and setup is performed through the serial control bus.
The SL11R 16-bit processor has direct access to the control port and the camera operation is dependent on commands passed
from the USB Host to the SL11R.
Raw video data from the Camera is input to the SL11R on the 8-bit video data bus (SD7-SD0) using a combination of clock and
control signals and 8 bit DMA. The signals include a clock (MCK0), Field Index (FI), Sync and blanking signals (SYNC, PBLK),
and Drive signals (VD and HD). The DMA Engine is used to transfer the image from the 8-bit bus (SD7-SD0) to external DRAM
port. The software uses the Fast DMA configuration registers.
Note:
5.4.1
The camera sends an 8 bit data bus with a number of control signals. The SL11R uses the following control signals to acquire
the video data:
The first 8 bytes of Data is discarded from the video stream starting at the assertion of each PBLK. After PBLK is de-asserted,
7 more bytes of data are taken. The Video Control and Status Register allows the acquisition of video images and provides power
and reset controls for the camera.
Document #: 38-08006 Rev. **
• The PWM Interface is not supported in this mode.
• Any other unused IO pins can be used as GPIO pins under control of the GPIO mode.
RD7-0: Read Data. Reading this register initiates a read cycle on the serial bus and sets the Busy bit = ’1’ in the Status
Register (C048H). Read data is valid when the Busy bit in the status register is cleared to ’0’.
MCK0
FI
VD
PBLK
SD7-SD0
N_RST
D7-5
D4
D3
D2
DVC 8-bit DMA Mode
Video Status Register(0xC06E: Read Only)
RD7
D7
D7
0
From Camera
From Camera
From Camera
From Camera
From Camera
To Camera
Reserved
VRST
P-CONT
Reserved
RD6
D6
D6
0
RD5
Pixel Clock = 9.534965MHz
Field Index. Contains 1 Vertical sweep + Blank
Active During Vertical Sweep.
Active during Horizontal sweep.
CCD Video data.
Active Low Reset
Always = '0'
When set = '1' powers up camera.
Always = '0'.
Video Reset. '0' Resets Camera (See Note).
D5
D5
0
VRST
RD4
D4
D4
Read OnlyAddress C04CH
P-CONT
RD3
D3
D3
D2
RD2
0
D2
D1
F
RD1
D1
SC
D0
RD0
D0
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SL11R