EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 256

• Manufacturer Part Number: EP1S20F672I7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672I7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Timing Model
4–86
Stratix Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
LVDS
HyperTransport
technology
Table 4–123. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1,
2, 3, 4] Pins in Wire-Bond Packages (Part 2 of 2)
Differential SSTL-2 outputs are only available on column clock pins.
These parameters are only available on row I/O pins.
SSTL-2 in maximum drive strength condition. See
more information on exact loading conditions for each I/O standard.
SSTL-2 in minimum drive strength with
SSTL-2 in minimum drive strength with > 10pF output load condition.
Differential SSTL-2 outputs are only supported on column clock pins.
I/O Standard
(2)
Tables 4–120
(2)
through 4–123:
-6 Speed
Grade
400
420
-7 Speed
Grade
311
400
≤
10pF output load condition.
-8 Speed
Grade
Table 4–101 on page 4–62
311
400
Altera Corporation
January 2006
MHz
MHz
Unit
for