EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 121
EP1S20F672I7
Manufacturer Part Number
EP1S20F672I7
Description
IC STRATIX FPGA 20K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F672I7
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
426
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F672I7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S20F672I7N
Manufacturer:
ALTERA20
Quantity:
212
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Figure 2–61. Column I/O Block Connection to the Interconnect
Notes to
(1)
(2)
Altera Corporation
July 2005
The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0],
four clocks io_bclk[3..0], and four clear signals io_bclr[3..0].
The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications
io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables
io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear
signals io_cclr[5..0].
Local Interconnect
Figure
Signals from I/O
Interconnect (1)
from Logic Array (2)
R4, R8 & R24
Interconnects
16 Control
I/O Block
2–61:
Control Signals
42 Data &
Interconnect
LAB
LAB Local
16
Vertical I/O Block
C4, C8 & C16
Interconnects
42
LAB
IO_datain[3:0]
Stratix Device Handbook, Volume 1
LAB
Vertical I/O
Block Contains
up to Six IOEs
io_clk[7..0]
Stratix Architecture
I/O Interconnect
2–107
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