EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 136
![IC STRATIX FPGA 20K LE 672-FBGA](/photos/6/73/67394/ds-672fbga205-2_0_sml.jpg)
EP1S20F672I7
Manufacturer Part Number
EP1S20F672I7
Description
IC STRATIX FPGA 20K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F672I7
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
426
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F672I7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S20F672I7N
Manufacturer:
ALTERA20
Quantity:
212
- Current page: 136 of 276
- Download datasheet (4Mb)
I/O Structure
2–122
Stratix Device Handbook, Volume 1
Programmable Pull-Up Resistor
Each Stratix device I/O pin provides an optional programmable pull-up
resistor during user mode. If this feature is enabled for an I/O pin, the
pull-up resistor (typically 25 kΩ) weakly holds the output to the V
level of the output pin’s bank.
the weak pull-up resistor feature.
Advanced I/O Standard Support
Stratix device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Note to
(1)
I/O pins
CLK[15..0]
FCLK
FPLL[7..10]CLK
Configuration pins
JTAG pins
Table 2–30. Programmable Weak Pull-Up Resistor Support
LVTTL
LVCMOS
1.5 V
1.8 V
2.5 V
3.3-V PCI
3.3-V PCI-X 1.0
3.3-V AGP (1× and 2×)
LVDS
LVPECL
3.3-V PCML
HyperTransport
Differential HSTL (on input/output clocks only)
Differential SSTL (on output column clock pins only)
GTL/GTL+
1.5-V HSTL Class I and II
TDO pins do not support programmable weak pull-up resistors.
Table
2–30:
Pin Type
Table 2–30
Programmable Weak Pull-Up Resistor
shows which pin types support
v
v
v
Altera Corporation
(1)
July 2005
CCIO
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