EP3C5M164C7N Altera, EP3C5M164C7N Datasheet - Page 33

IC CYCLONE III FPGA 5K 164 MBGA

EP3C5M164C7N

Manufacturer Part Number
EP3C5M164C7N
Description
IC CYCLONE III FPGA 5K 164 MBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C5M164C7N

Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
106
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
164-MBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
106
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2559

Available stocks

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Manufacturer
Quantity
Price
Part Number:
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ALTERA
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Part Number:
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0
Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
Logic Array Blocks
Logic Array Blocks
Topology
Figure 2–4. Cyclone III Device Family LAB Structure
© December 2009
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
Altera Corporation
Logic array blocks (LABs) contain groups of LEs.
Each LAB consists of the following features:
The local interconnect transfers signals between LEs in the same LAB. Register chain
connections transfer the output of one LE register to the adjacent LE register in a LAB.
The Quartus II Compiler places associated logic in a LAB or adjacent LABs, allowing
the use of local and register chain connections for performance and area efficiency.
Figure 2–4
16 LEs
LAB control signals
LE carry chains
Register chains
Local interconnect
shows the LAB structure for the Cyclone III device family.
LAB
Local Interconnect
Row Interconnect
Cyclone III Device Handbook, Volume 1
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
Column
Interconnect
2–5

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