EP3C5M164C7N Altera, EP3C5M164C7N Datasheet - Page 122

IC CYCLONE III FPGA 5K 164 MBGA

EP3C5M164C7N

Manufacturer Part Number
EP3C5M164C7N
Description
IC CYCLONE III FPGA 5K 164 MBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C5M164C7N

Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
106
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
164-MBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
106
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2559

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C5M164C7N
Manufacturer:
ALTERA
Quantity:
526
Part Number:
EP3C5M164C7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP3C5M164C7N
Manufacturer:
ALTERA
0
6–22
Table 6–7. Chapter Revision History (Part 2 of 3)
Cyclone III Device Handbook, Volume 1
May 2008
Date
Version
2.0
Changes include addition of BLVDS information.
Added an introduction to “I/O Element Features” section.
Updated “Slew Rate Control” section.
Updated “Programmable Delay” section.
Updated Table 6–1 with BLVDS information.
Updated Table 6–2.
Updated “PCI-Clamp Diode” section.
Updated “LVDS Transmitter Programmable Pre-Emphasis” section.
Updated “On-Chip Termination with Calibration” section and added new
Figure 6–9.
Updated Table 6–3 title.
Updated Table 6–4 unit.
Updated “I/O Standards” section and Table 6–5 with BLVDS information and
added (Note 5).
Updated “Differential I/O Standard Termination” section with BLVDS
information.
Updated “I/O Banks” section.
Updated (Note 2) and added (Note 7) and BLVDS information to
Figure 6–15.
Updated (Note 2) and added BLVDS information to Table 6–6.
Added MBGA package information to Table 6–7.
Deleted Table 6-8.
Updated “High-Speed Differential Interfaces” section with BLVDS
information.
Updated “Differential Pad Placement Guidelines” section and added new
Figure 6–16.
Updated “V
Figure 6–17.
Updated Table 6–11.
Added new “DCLK Pad Placement Guidelines” section.
Updated “DC Guidelines” section.
REF
Pad Placement Guidelines” section and added new
Chapter 6: I/O Features in the Cyclone III Device Family
Changes Made
© December 2009 Altera Corporation
Chapter Revision History

Related parts for EP3C5M164C7N