EP3C5M164C7N Altera, EP3C5M164C7N Datasheet - Page 131

IC CYCLONE III FPGA 5K 164 MBGA

EP3C5M164C7N

Manufacturer Part Number
EP3C5M164C7N
Description
IC CYCLONE III FPGA 5K 164 MBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C5M164C7N

Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
106
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
164-MBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
106
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2559

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0
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
High-Speed I/O Standards Support
LVDS I/O Standard Support in the Cyclone III Device Family
© December 2009
f
Altera Corporation
Table 7–4
Cyclone III LS devices.
Table 7–4. Cyclone III LS Devices Migratable Differential Channels
This section provides information about the high-speed I/O standards supported in
the Cyclone III device family.
The LVDS I/O standard is a high-speed, low-voltage swing, low power, and general
purpose I/O interface standard. The Cyclone III device family meets the
ANSI/TIA/EIA-644 standard with the following exceptions:
For more information about the LVDS I/O standard electrical specifications in the
Cyclone III device family, refer to the
Device Data Sheet
Note to
(1) The migratable differential channels for Cyclone III devices are not directly migratable to Cyclone III LS devices
Package
The maximum differential output voltage (V
maximum V
The input voltage range is reduced to the range of 1.0 V to 1.6 V, 0.5 V to 1.85 V, or
0 V to 1.8 V based on different frequency ranges. The ANSI/TIA/EIA-644
specification supports an input voltage range of 0 V to 2.4 V.
U484
Type
F484
F780
and vice versa.
Table
lists the numbers of differential channels that can be migrated in
7–4:
EP3CLS70 and EP3CLS100
EP3CLS70 and EP3CLS100
EP3CLS70 and EP3CLS150
EP3CLS70 and EP3CLS200
EP3CLS100 and EP3CLS150
EP3CLS100 and EP3CLS200
EP3CLS150 and EP3CLS200
EP3CLS70 and EP3CLS100
EP3CLS70 and EP3CLS150
EP3CLS70 and EP3CLS200
EP3CLS100 and EP3CLS150
EP3CLS100 and EP3CLS200
EP3CLS150 and EP3CLS200
Migration between Devices
OD
chapters.
for ANSI specification is 450 mV.
Cyclone III Device Data Sheet
User I/O
101
101
169
169
169
169
169
169
71
71
71
71
75
OD
) is increased to 600 mV. The
Migratable Channels
Clock
Input
Cyclone III Device Handbook, Volume 1
(Note 1)
8
8
8
8
8
8
8
8
8
8
8
8
8
and
Output
Clock
4
4
4
4
4
4
4
4
4
4
4
4
4
Cyclone III LS
Total
113
113
181
181
181
181
181
181
83
83
87
83
83
7–7

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