EP3C5M164C7N Altera, EP3C5M164C7N Datasheet - Page 112

• Manufacturer Part Number: EP3C5M164C7N
• Description: IC CYCLONE III FPGA 5K 164 MBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5M164C7N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 106
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 164-MBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 5136
• # I/os (max): 106
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 5136
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 164
• Package Type: MBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2559

6–12
Table 6–4. Cyclone III Device Family Supported I/O Standards and Constraints (Part 1 of 2)
Cyclone III Device Handbook, Volume 1
3.3-V LVTTL,
3.3-V LVCMOS
3.0-V LVTTL,
3.0-V LVCMOS
2.5-V LVTTL /
LVCMOS
1.8-V LVTTL /
LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I,
SSTL-2 Class II
SSTL-18 Class I,
SSTL-18 Class II
HSTL-18 Class I,
HSTL-18 Class II
HSTL-15 Class I,
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
PCI and PCI-X
Differential SSTL-2
Class I or Class II
Differential SSTL-18
Class I or Class II
Differential HSTL-18
Class I or Class II
Differential HSTL-15
Class I or Class II
Differential HSTL-12
Class I or Class II
PPDS
LVDS
I/O Standard
(7)
(3)
(1)
(1)
(6)
Single-ended JESD8-B
Single-ended JESD8-B
Single-ended JESD8-5
Single-ended JESD8-7
Single-ended JESD8-11
Single-ended JESD8-12A
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Single-ended
Differential
(2)
Differential
(2)
Differential
(2)
Differential
(2)
Differential
(2)
Differential
Differential
Table 6–4
I/O pins support them.
Type
lists I/O standards supported by the Cyclone III device family and which
JESD8-9A
JESD815
JESD8-6
JESD8-6
JESD8-16A
JESD8-16A
JESD8-9A
JESD815
JESD8-6
JESD8-6
JESD8-16A
Standard
Support
—
—
—
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
1.8/1.5
1.8/1.5
Input
1.2
2.5
1.8
1.8
1.5
1.2
1.2
3.0
2.5
1.8
1.8
1.5
1.2
2.5
V
—
—
—
—
—
—
C CIO
Level (in V)
Output
3.3
3.0
2.5
1.8
1.5
1.2
2.5
1.8
1.8
1.5
1.2
1.2
3.0
2.5
1.8
1.8
1.5
1.2
2.5
2.5
—
—
—
—
—
Chapter 6: I/O Features in the Cyclone III Device Family
CLK,
DQS
Top and Bottom I/O Pins
v
v
v
v
v
v
v
v
v
v
v
v
v
—
v
—
v
—
v
—
v
—
v
—
v
PLL_OUT
© December 2009 Altera Corporation
v
v
v
v
v
v
v
v
v
v
v
v
v
v
—
v
—
v
v
v
v
v
—
—
—
User
Pins
I/O
v
v
v
v
v
v
v
v
v
v
v
v
v
—
—
—
—
—
—
—
—
—
—
v
v
CLK,
Left and Right
DQS
I/O Standards
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
—
—
—
—
—
—
—
I/O Pins
User I/O
Pins
v
v
v
v
v
v
v
v
v
v
v
—
v
—
—
—
—
—
—
—
—
—
—
v
v