EPM1270F256C3 Altera, EPM1270F256C3 Datasheet - Page 9
![IC MAX II CPLD 1270 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM1270F256C3
Manufacturer Part Number
EPM1270F256C3
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270F256C3
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
3.01205GHz
Propagation Delay Time
6.2ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1321
EPM1270F256C3
EPM1270F256C3
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA
Quantity:
162
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Introduction
Functional Description
© October 2008 Altera Corporation
MII51002-2.2
This chapter describes the architecture of the MAX II device and contains the
following sections:
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MAX
implement custom logic. Row and column interconnects provide signal interconnects
between the logic array blocks (LABs).
The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a
small unit of logic providing efficient implementation of user logic functions. LABs
are grouped into rows and columns across the device. The MultiTrack interconnect
provides fast granular timing delays between LABs. The fast routing between LEs
provides minimum timing delay for added levels of logic versus globally routed
interconnect structures.
The MAX II device I/O pins are fed by I/O elements (IOE) located at the ends of LAB
rows and columns around the periphery of the device. Each IOE contains a
bidirectional I/O buffer with several advanced features. I/O pins support Schmitt
trigger inputs and various single-ended standards, such as 66-MHz, 32-bit PCI, and
LVTTL.
MAX II devices provide a global clock network. The global clock network consists of
four global clock lines that drive throughout the entire device, providing clocks for all
resources within the device. The global clock lines can also be used for control signals
such as clear, preset, or output enable.
“Functional Description” on page 2–1
“Logic Array Blocks” on page 2–4
“Logic Elements” on page 2–6
“MultiTrack Interconnect” on page 2–12
“Global Signals” on page 2–16
“User Flash Memory Block” on page 2–18
“MultiVolt Core” on page 2–22
“I/O Structure” on page 2–23
®
II devices contain a two-dimensional row- and column-based architecture to
2. MAX II Architecture
MAX II Device Handbook