EPM1270F256C3 Altera, EPM1270F256C3 Datasheet - Page 78
![IC MAX II CPLD 1270 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM1270F256C3
Manufacturer Part Number
EPM1270F256C3
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270F256C3
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
3.01205GHz
Propagation Delay Time
6.2ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1321
EPM1270F256C3
EPM1270F256C3
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA
Quantity:
162
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
5–20
Table 5–24. EPM570 Global Clock External I/O Timing Parameters
Table 5–25. EPM1270 Global Clock External I/O Timing Parameters
MAX II Device Handbook
Symbol
f
Note to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input
t
t
t
t
t
t
t
t
f
Note to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
CNT
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
Symbol
pin maximum frequency.
clock input pin maximum frequency.
Table
Table
Maximum
global clock
frequency for
16-bit counter
Parameter
5–24:
5–25:
Worst case pin-to-pin
delay through 1 look-up
table (LUT)
Best case pin-to-pin
delay through 1 LUT
Global clock setup time
Global clock hold time
Global clock to output
delay
Global clock high time
Global clock low time
Minimum global clock
period for
16-bit counter
Maximum global clock
frequency for 16-bit
counter
Parameter
Table 5–25
Condition
—
shows the external I/O timing parameters for EPM1270 devices.
Min
—
–3 Speed
Condition
Grade
10 pF
10 pF
10 pF
—
—
—
—
—
—
304.0
Max
(1)
MAX II / MAX IIG
Min
—
–4 Speed
Min
166
166
Grade
–3 Speed Grade
1.2
3.3
2.0
—
—
—
0
247.5
Max
304.0
Max
6.2
3.7
4.6
(Part 2 of 2)
Min
—
—
—
—
—
—
–5 Speed
Grade
(1)
201.1
MAX II / MAX IIG
Max
–4 Speed Grade –5 Speed Grade
Min
216
216
1.5
2.0
4.0
—
—
—
0
Min
—
Chapter 5: DC and Switching Characteristics
–6 Speed
Grade
247.5
Max
8.1
4.8
5.9
—
—
—
—
—
184.1
Max
© August 2009 Altera Corporation
Timing Model and Specifications
Min
—
Min
266
266
1.9
2.0
5.0
–7 Speed
—
—
—
MAX IIZ
0
Grade
123.5
Max
201.1
Max
10.0
5.9
7.3
—
—
—
—
—
Min
—
–8 Speed
Grade
MHz
Unit
ns
ns
ns
ns
ns
ps
ps
ns
118.3 MHz
Max
Unit