EPM1270F256C3 Altera, EPM1270F256C3 Datasheet - Page 85
![IC MAX II CPLD 1270 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM1270F256C3
Manufacturer Part Number
EPM1270F256C3
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270F256C3
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
3.01205GHz
Propagation Delay Time
6.2ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1321
EPM1270F256C3
EPM1270F256C3
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA
Quantity:
162
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 5: DC and Switching Characteristics
Document Revision History
Document Revision History
Table 5–35. Document Revision History (Part 1 of 2)
© August 2009 Altera Corporation
August 2009,
version 2.5
November 2008,
version 2.4
October 2008,
version 2.3
July 2008,
version 2.2
March 2008,
version 2.1
December 2007,
version 2.0
December 2006,
version 1.8
July 2006,
version 1.7
February 2006,
version 1.6
November 2005,
version 1.5
August 2005,
version 1.4
Date and Revision
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Table 5–35
Added
Updated
Table
Table
Table
Updated Table 5–2.
Updated “Internal Timing Parameters” section.
Updated New Document Format.
Updated Figure 5–1.
Updated Table 5–14 , Table 5–23 , and Table 5–24.
Added (Note 5) to Table 5–4.
Updated (Note 3) and (4) to Table 5–1.
Updated Table 5–2 and added (Note 5).
Updated ICCSTANDBY and ICCPOWERUP information and added
IPULLUP information in Table 5–4.
Added (Note 1) to Table 5–10.
Updated Figure 5–2.
Added (Note 1) to Table 5–13.
Updated Table 5–13 through Table 5–24, and Table 5–27 through
Table 5–30.
Added tCOMB information to Table 5–15.
Updated Figure 5–6.
Added “Referenced Documents” section.
Added note to Table 5–1.
Added document revision history.
Minor content and table updates.
Updated “External Timing I/O Delay Adders” section.
Updated Table 5–29.
Updated Table 5–30.
Updated Tables 5-2, 5-4, and 5-12.
Updated Figure 5-1.
Updated Tables 5-13, 5-16, and 5-26.
Removed Note 1 from Table 5-12.
5–17,
5–22,
5–32, and
Table
Table
shows the revision history for this chapter.
Table
Table
5–28,
5–2,
Table
5–18,
5–23,
Table
Table
5–33.
Table
Table
5–29, and
5–4,
Changes Made
5–19,
5–24,
Table
Table
Table
Table
5–14,
5–30.
5–20,
5–27,
Table
Table
Table
5–15,
5–21,
5–31,
Table
5–16,
Added information for
speed grade –8
Updated document with
MAX IIZ information.
Summary of Changes
MAX II Device Handbook
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5–27