EPM1270F256C3 Altera, EPM1270F256C3 Datasheet - Page 72
![IC MAX II CPLD 1270 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM1270F256C3
Manufacturer Part Number
EPM1270F256C3
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270F256C3
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
3.01205GHz
Propagation Delay Time
6.2ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1321
EPM1270F256C3
EPM1270F256C3
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA
Quantity:
162
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
5–14
Table 5–20. t
Table 5–21. UFM Block Internal Timing Microparameters (Part 1 of 3)
MAX II Device Handbook
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL /
LVCMOS
3.3-V PCI
t
t
t
t
t
t
t
t
Symbol
AC LK
AS U
AH
ADS
ADH
DCLK
DSS
DSH
Standard
Address register clock
period
Address register shift
signal setup to
address register clock
Address register shift
signal hold to address
register clock
Address register data
in setup to address
register clock
Address register data
in hold from address
register clock
Data register clock
period
Data register shift
signal setup to data
register clock
Data register shift
signal hold from data
register clock
XZ
1
IOE Microparameter Adders for Slow Slew Rate
Parameter
16 mA
14 mA
20 mA
8 mA
8 mA
4 mA
7 mA
The default slew rate setting for MAX II devices in the Quartus II design software is
“fast”.
Min
—
—
—
—
—
—
—
–3 Speed
Grade
Max
891
891
222
943
Min
206
206
161
100
100
–3 Speed
20
20
20
20
60
20
Grade
MAX II / MAX IIG
Min
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–4 Speed
Grade
MAX II / MAX IIG
Max
Min
100
100
–20
665
–20
665
717
210
–4 Speed
20
20
20
20
60
20
–4
Grade
Max
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–5 Speed
Grade
–247
–247
–231
Max
Min
100
100
438
438
490
258
–5 Speed
20
20
20
20
60
20
Grade
Max
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–6 Speed
Grade
Min Max Min Max Min Max
100
100
1,433
1,332
1,433
1,332
1,332
–6 Speed
20
20
20
20
60
20
Max
213
166
Grade
Chapter 5: DC and Switching Characteristics
—
—
—
—
—
—
—
—
Min
—
—
—
—
—
—
—
–7 Speed
MAX IIZ
Grade
100
100
–7 Speed
20
20
20
20
60
20
MAX IIZ
© August 2009 Altera Corporation
Grade
1,446
1,345
1,446
1,345
1,345
Max
208
161
Timing Model and Specifications
—
—
—
—
—
—
—
—
Min
—
—
—
—
—
—
—
–8 Speed
100
100
–8 Speed
20
20
20
20
60
20
Grade
Grade
1,454
1,348
1,454
1,348
1,348
Max
213
166
—
—
—
—
—
—
—
—
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns