EPM1270F256C3 Altera, EPM1270F256C3 Datasheet - Page 50
![IC MAX II CPLD 1270 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM1270F256C3
Manufacturer Part Number
EPM1270F256C3
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270F256C3
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
3.01205GHz
Propagation Delay Time
6.2ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1321
EPM1270F256C3
EPM1270F256C3
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA
Quantity:
162
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
3–8
Document Revision History
Table 3–5. Document Revision History
MAX II Device Handbook
Date and Revision
October 2008,
version 1.6
December 2007,
version 1.5
December 2006,
version 1.4
June 2005,
version 1.3
June 2005,
version 1.3
June 2004,
version 1.1
Changes Made
■
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■
■
■
■
■
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Table 3–5
Updated New Document Format.
Added warning note after
Updated
Added
Added document revision history.
Added text and Table 3-4.
Updated text on pages 3-5 to 3-8.
Corrected Figure 3-1. Added CFM acronym.
“Referenced Documents”
Table 3–3
shows the revision history for this chapter.
and
Table
Table
3–4.
3–1.
section.
Chapter 3: JTAG and In-System Programmability
Summary of Changes
© October 2008 Altera Corporation
Document Revision History
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