EPM1270F256C3 Altera, EPM1270F256C3 Datasheet - Page 74
![IC MAX II CPLD 1270 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM1270F256C3
Manufacturer Part Number
EPM1270F256C3
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270F256C3
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
3.01205GHz
Propagation Delay Time
6.2ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1321
EPM1270F256C3
EPM1270F256C3
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA
Quantity:
162
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
5–16
Table 5–21. UFM Block Internal Timing Microparameters (Part 3 of 3)
Figure 5–3. UFM Read Waveforms
MAX II Device Handbook
t
t
t
t
Symbol
OE
RA
OSC S
OSC H
Delay from data
register clock to data
register output
Maximum read
access time
Maximum delay
between the
OSC_ENA rising
edge to the
erase/program signal
rising edge
Minimum delay
allowed from the
erase/program signal
going low to
OSC_ENA signal
going low
Parameter
OSC_ENA
Program
DRDout
DRShft
ARShft
DRDin
ARClk
ARDin
DRClk
Erase
Figure 5–3
UFM block timing parameters shown in
Busy
t
t
ASU
ADS
through
Min
180
250
250
–3 Speed
—
Grade
t
ACLK
Max
—
65
—
—
9 Address Bits
Figure 5–5
MAX II / MAX IIG
Min
180
250
250
–4 Speed
—
Grade
Max
—
65
—
—
t
t
ADH
show the read, program, and erase waveforms for
AH
t
DCO
t
DSS
Min
180
250
250
–5 Speed
—
Grade
t
DCLK
Table
Max
—
65
—
—
16 Data Bits
5–21.
Min Max Min Max Min Max
180
250
250
–6 Speed
—
Grade
Chapter 5: DC and Switching Characteristics
—
65
—
—
t
DSH
180
250
250
–7 Speed
—
MAX IIZ
© August 2009 Altera Corporation
Grade
Timing Model and Specifications
—
65
—
—
180
250
250
–8 Speed
—
Grade
—
65
—
—
Unit
ns
ns
ns
ns