EPM1270F256C3 Altera, EPM1270F256C3 Datasheet - Page 53
![IC MAX II CPLD 1270 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM1270F256C3
Manufacturer Part Number
EPM1270F256C3
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270F256C3
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Family Name
MAX II
# Macrocells
980
Frequency (max)
3.01205GHz
Propagation Delay Time
6.2ns
Number Of Logic Blocks/elements
127
# I/os (max)
212
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1321
EPM1270F256C3
EPM1270F256C3
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA
Quantity:
162
Part Number:
EPM1270F256C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Hot Socketing Feature Implementation in MAX II Devices
Figure 4–1. Hot Socketing Circuit Block Diagram for MAX II Devices
© October 2008 Altera Corporation
f
1
Make sure that the V
SRAM download has completed.
Each I/O and clock pin has the circuitry shown in
The POR circuit monitors V
until the device has completed its flash memory configuration of the SRAM logic. The
weak pull-up resistor (R) from the I/O pin to V
keep the I/O pins from floating. The 3.3-V tolerance control circuit permits the I/O
pins to be driven by 3.3 V before V
I/O pins from driving out when the device is not fully powered or operational. The
hot socket circuit prevents I/O pins from internally powering V
driven by external signals before the device is powered.
For information about 5.0-V tolerance, refer to the
Voltage Systems
Figure 4–2
This design ensures that the output buffers do not drive when V
V
voltage spikes during hot insertion. The V
tolerant circuit capacitance.
Resistor
Pull-Up
CCINT
Weak
PAD
or if the I/O pad voltage is higher than V
shows a transistor-level cross section of the MAX II device I/O buffers.
chapter in the MAX II Device Handbook.
V
CCINT
CCIO
is within the recommended operating range even though
CCINT
and V
Input Buffer
to Logic Array
CCIO
Tolerance
Voltage
Control
CCIO
and/or V
voltage levels and keeps I/O pins tri-stated
PAD
Output Enable
leakage current charges the 3.3-V
CCIO
CCIO
CCINT
Using MAX II Devices in Multi-
Figure
. This also applies for sudden
is enabled during download to
Hot Socket
are powered, and it prevents the
Power On
Monitor
Reset
4–1.
CCIO
CCIO
is powered before
and V
MAX II Device Handbook
CCINT
when
4–3