LE58QL063HVC Zarlink, LE58QL063HVC Datasheet - Page 83

• Manufacturer Part Number: LE58QL063HVC
• Description: SLIC 4-CH 3.3V 64-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of LE58QL063HVC

• Package: 64LQFP
• Number Of Channels Per Chip: 4
• Polarity Reversal: Yes
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

M
M
In the QLSLAC device, a coefficient, h
where Cxy is 1 bit (MSB) and mxy is 3 bits. Each CSD coefficient is broken down as follows:
Cxy
mxy
000:
001:
010:
011:
100:
101:
110:
111:
y
x
Thus, C13 m13 represents the sign and the relative shift position for the first (most significant) binary 1 in the 4th (h
The number of CSD coefficients, N, is limited to 4 in the GR, GX, R, X, and Z filters; 4 in the IIR part of the B filter; 3 in the FIR
part of the B filter; and 2 in the post-gain factor of the Z-IIR filter. The GX filter coefficient equation is slightly different from the
other filters.
Please refer to Summary of MPI Commands on
User Test States and Operating Conditions
The QLSLAC device supports testing by providing test states and special operating conditions as shown in Figure 23 (see
Operating Conditions register).
Cutoff Transmit Path (CTP): When CTP = 1, DX and TSC are High impedance and the transmit time slot does not exist. This
state takes precedence over the TSA Loopback (TLB) and Full Digital Loopback (FDL) states.
Cutoff Receive Path (CRP): When CRP = 1, the receive signal is forced to 0 just ahead of the low pass filter (LPF) block. This
state also blocks Full Digital Loopback (FDL), the 1 kHz receive tone, and the B-filter path.
High Pass Filter Disable (HPF): When HPF = 1, all of the High pass and notch filters in the transmit path are disabled.
Lower Receive Gain (LRG): When LRG = 1, an extra 6.02 dB of loss is inserted into the receive path.
Arm Transmit Interrupt (ATI) and Read Transmit PCM Data (PCM/MPI mode only): The read transmit PCM data command,
Command CDh, can be used to read transmit PCM data through the microprocessor interface. If the ATI bit is set, an interrupt
will be generated whenever new transmit data appears in the channel and will be cleared when the data is read. When combined
with Tone Generation and Loopback states, this allows the microprocessor to test channel integrity.
Interface Loopback (ILB): When ILB = 1, data from the receive/downstream path is looped back to the transmit/Upstream path.
Any other data in the transmit path is overwritten.
Full Digital Loopback (FDL): When FDL = 1, the VOUT output is turned off and the analog output voltage is routed to the input
of the transmit path, replacing the voltage from VIN. The AISN path is temporarily turned off. This test mode can also be entered
by writing the code 10000 into the AISN register.
1 kHz Receive Tone (TON): When TON = 1, a 1 kHz digital mW is injected into the receive path, replacing any receive or
downstream signal.
h
3
4
iGX
= m1 + m2 + m3
= m1 + m2 + m3 + m4
=
1
is the sign bit (0 = positive, 1 = negative).
is the 3-bit shift code. It is encoded as a binary
number as follows:
0 shifts
1 shifts
2 shifts
3 shifts
4 shifts
5 shifts
6 shifts
7 shifts
is the coefficient number (the i in h
next most significant binary 1 is represented by x = 2, and so on.
is the position of this CSD coefficient within the h
+
h
i
B
B
3
4
= C1 • C2 • C3
= C1 • C2 • C3 • C4
i
, consists of N CSD coefficients, each being made up of 4 bits and formatted as Cxy mxy,
i
).
page 44
Equation 8
Zarlink Semiconductor Inc.
for complete details on programming the coefficients.
i
coefficient. The most significant binary 1 is represented by x = 1. The
83
3
) coefficient.