LE58QL063HVC Zarlink, LE58QL063HVC Datasheet - Page 63

• Manufacturer Part Number: LE58QL063HVC
• Description: SLIC 4-CH 3.3V 64-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of LE58QL063HVC

• Package: 64LQFP
• Number Of Channels Per Chip: 4
• Polarity Reversal: Yes
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

For the 64-pin package, this octet is defined as:
<---------------- Downstream SC Octet ------------------>
|<------------------- C/I Field ------------------->|
A: Channel Address Bit
C5
C7
C = 1 or 2, the channel selected by A
If the QLSLAC device’s programmable I/O ports, CD1, CD2, and C3 are programmed for Input mode, then data is obtained
through the Upstream C/I channel.
Figure 27 shows the transmission protocol for the downstream C/I. Whenever the received pattern of C/I bits 6–1 is different from
the pattern currently in the C/I input register, the new pattern is loaded into a secondary C/I register and a latch is set. When the
next pattern is received (in the following frame) while the latch is set, the following rules apply:
1.
2.
3.
MSB
C
C
7
A
–CD2
–C3
0: Selects CH 1 or 3 as the downstream data destination
1: Selects CH 2 or 4 as the downstream data destination
If the received pattern corresponds to the pattern in the secondary register, the new pattern is loaded into the C/I register for
the addressed channel and the latch is reset. The updated C/I register data appears at the programmable I/O pins of the
device one frame (125 µs) later if they are programmed as outputs.
If the received pattern is different from the pattern in the secondary register and different from the pattern currently in the C/
I register, the newly received pattern is loaded into the secondary C/I register and the latch remains set. The data at the PI/
O port remains unchanged.
If the received pattern is the same as the pattern currently in the C/I register, the C/I register is unchanged and the latch is
reset.
C
C7
: SLIC device output latch bits 7–3 of the channel selected by A. (64-pin package)
C
6
C
CD1
C
C6
: SLIC device output latch bits 5–1 for CHx of the channel selected by A. (44-pin package)
5
C
C5
4
Receive New C/I Code
Receive New C/I Code
C
Store in S
C4
Figure 27. Security Procedure for C/I Downstream Bytes
3
= S ?
= I ?
= I ?
C
No
No
No
C3
2
C
Yes
Yes
Yes
MR
1
Zarlink Semiconductor Inc.
LSB
MX
0
63
I: C/I Register Contents
S: C/I Secondary Register Contents
Load C/I Register
with New Code