LE58QL063HVC Zarlink, LE58QL063HVC Datasheet - Page 43

• Manufacturer Part Number: LE58QL063HVC
• Description: SLIC 4-CH 3.3V 64-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of LE58QL063HVC

• Package: 64LQFP
• Number Of Channels Per Chip: 4
• Polarity Reversal: Yes
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

Commands are provided to read values from the following channel monitors:
Commands are provided to assign values to the following global chip parameters:
Commands are provided to read values from the following global chip status monitors:
Microprocessor Interface Description
When PCM/MPI mode is selected via the CS/PG and DCLK/S0 pins, a microprocessor can be used to program the QLSLAC
device and control its operation using the Microprocessor Interface (MPI). Data programmed previously can be read out for
verification.
The following description of the MPI (Microprocessor Interface) is valid for channels 1– 4. If desired, multiple channels can be
programmed simultaneously with identical information by setting multiple Channel Enable bits. Channel enables are contained
in the Channel Enable register and are written or read using Command 4A/4Bh. If multiple Channel Enable bits are set for a read
operation, only data from the first enabled channel will be read.
The MPI physically consists of a serial data input/output (DIO), a data clock (DCLK), and a chip select (CS). Individual Channel
Enable bits EC1, EC2, EC3, and EC4 are stored internally in the Channel Enable register of the QLSLAC device. The serial input
consists of 8-bit commands that can be followed with additional bytes of input data, or can be followed by the QLSLAC device
sending out bytes of data. All data input and output is MSB (D7) first and LSB (D0) last. All data bytes are read or written one at
a time, with CS going High for at least a minimum off period before the next byte is read or written. Only a single channel should
be enabled during read commands.
Table 5. Channel Monitors
Table 6. Global Chip Parameters
Table 7. Global Chip Status Monitors
Parameter
CD1–C5
CMODE
Monitor
SMODE
VMODE
Monitor
MCDx
CONF
DPCK
CFAIL
CD1B
XDAT
CSEL
INTM
CDx
RCS
CHP
ECH
DSH
RCN
TCS
RBE
EE1
E1P
EC
XE
DT
C
C
Read SLIC device Inputs
Multiplexed SLIC device Input
Transmit PCM data
Transmit PCM Clock Edge
Receive Clock Slot
Transmit Clock Slot
Interrupt Output Drive Mode
Chopper Clock Frequency
Enable Chopper Clock Output
Select Signaling on the PCM Highway
Select Master Clock Mode
Select Master Clock Frequency
Robbed Bit Enable
VOUT Mode
Channel Enable Register
Debounce Time for CD1
Enable E1 Output
E1 Polarity
Double PCLK Operation
Interrupt Mask Register
Real Time Data Register
Clock Failure Bit
Revision Code Number
Configuration (0000)
Device Type (10)
Description
Description
Description
Zarlink Semiconductor Inc.
43
C8/C9h
C8/C9h
C8/C9h
C8/C9h
C8/C9h
6C/6Dh
4A/4Bh
4A/4Bh
4A/4Bh
4D/4Fh
44/45h
44/45h
44/45h
46/47h
46/47h
46/47h
46/47h
46/47h
54/55h
CDh
MPI
53h
53h
MPI
MPI
73h
—
—
SOP 13, C/I
SOP 10
SOP 10
SOP 11
SOP 11
SOP 11
SOP 11
SOP 14
SOP 6
SOP 6
SOP 9
SOP 8
TOP 1
GCI
GCI
GCI
CIC
CIC
—
—
—
—
—
—
—
—
—
—