LE58QL063HVC Zarlink, LE58QL063HVC Datasheet - Page 72

• Manufacturer Part Number: LE58QL063HVC
• Description: SLIC 4-CH 3.3V 64-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of LE58QL063HVC

• Package: 64LQFP
• Number Of Channels Per Chip: 4
• Polarity Reversal: Yes
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

SOP 7. Write/Read Configuration Register 3 (CR3), Operating Functions
RSVD:
A-law/µ-law
GR filter
GX filter
X filter
R filter
Z filter
B filter
*Power Up and Hardware Reset (RST) Value = 00h
SOP 8. Write/Read Configuration Register 4 (CR4), SLIC Device I/O Direction and Status Bits
Pins CD1, CD2 and C3 through C5 are set to Input or Output modes individually.
RSVD:
Channel Status (Read only, write as 0)
Clock Fail (Read only, write as 0; Global status bit)
The CFAIL bit is universal for the QLSLAC device and is independent of the channel addressed.
IOD1–IOD5
Command
I/O Data
Command
I/O Data
GCI Command
(60/61h)
Operating Functions (Configuration Register 3, CR3)
GCI Command
(54/55h)
SLIC Device I/O Direction and Status Bits (Configuration Register 4, CR4)
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
A/µ = 0*
A/µ = 1
EGR = 0*
EGR = 1
EGX = 0*
EGX = 1
EX = 0*
EX = 1
ER = 0*
ER = 1
EZ = 0*
EZ = 1
EB = 0*
EB = 1
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
CSTAT = 0
CSTAT = 1
CFAIL = 0
CFAIL = 1
Programmable I/O direction control (CD1, CD2, C3, C4, C5 pins)
*0 = Pin is set as an input port
1 = Pin is set as an output port
A-law coding
µ-law coding
GR filter default coefficients used:
GR filter programmed coefficients used
GX filter default coefficients used
GX filter programmed coefficients used
X filter default coefficients used
X filter programmed coefficients used
R filter default coefficients used
R filter programmed coefficients used
Z filter default coefficients used
Z filter programmed coefficients used
B filter default coefficients used
B filter programmed coefficients used
Channel is inactive (Standby mode)
Channel is active
The internal clock is synchronized to frame sync
The internal clock is not synchronized to frame sync
RSVD
RSVD
D
0
D
7
0
7
Zarlink Semiconductor Inc.
CSTAT
D
A/µ
D
1
1
6
6
72
CFAIL
EGR
D
D
0
1
5
5
IOD5
EGX
D
D
1
0
4
4
IOD4
EX
D
D
0
0
3
3
IOD3
ER
D
D
0
1
2
2
IOD2
EZ
D
D
0
0
1
1
IOD1
R/W
R/W
EB
D
D
0
0