LE58QL063HVC Zarlink, LE58QL063HVC Datasheet
LE58QL063HVC
Specifications of LE58QL063HVC
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LE58QL063HVC Summary of contents
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... ORDERING INFORMATION Device Package (Green) Le58QL061FJC 44-pin PLCC Le58QL061BVC 44-pin TQFP Le58QL063HVC 64-pin LQFP 1. The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. 2. For delivery using a tape and reel packing system, add a "T" suffix to the OPN (Ordering Part Number) when placing an order ...
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... PCM and GCI State Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Channel Enable (EC) Register (PCM/MPI Mode .31 SLIC Device Control and Data Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Clock Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 E1 Multiplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Debounce Filters Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Real-Time Data Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Inactive State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Chopper Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2 Zarlink Semiconductor Inc. ...
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... Write/Read IIR Z Filter Coefficients (IIR only .58 C8/C9h Write/Read Debounce Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 CDh Read Transmit PCM Data (PCM/MPI Mode Only .59 E8/E9h Write/Read Ground Key Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 GENERAL CIRCUIT INTERFACE (GCI) SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 GCI General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 GCI Format and Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3 Zarlink Semiconductor Inc. ...
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... General Description of CSD Coefficients .82 User Test States and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 A-Law and µ-Law Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 APPLICATION CIRCUIT .87 LINE CARD PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 PHYSICAL DIMENSIONS .88 44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 44-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 64-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Revision .91 Revision .91 Revision .91 Revision .91 Revision .91 Revision .91 Revision .91 4 Zarlink Semiconductor Inc. ...
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... Table 8. GCI Channel Assignment Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Table 9. Generic Byte Transmission Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Table 10. Byte Transmission Sequence for TOP Command .69 Table 11. General Transmission Sequence of SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Table 12. Generic Transmission Sequence for COP Command .75 Table 13. A-Law: Positive Input Values .84 Table 14. µ-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5 Zarlink Semiconductor Inc. ...
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... TSA block. page 7. The Le58QL061, with a single PCM highway, is available in the 44-pin Chopper Clock per Channel Five I/O No Five I/O Yes Two Output 6 Zarlink Semiconductor Inc. ™ devices. In PCM/MPI mode, each channel has Package Part Number 44-Pin PLCC/TQFP Le58QL061VC, JC 64-Pin LQFP Le58QL063VC ...
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... VIN 1 VOUT 2 VIN 2 VCCA VREF AGND VIN 3 VOUT 3 VIN 4 VOUT Le58QL061JC 12 44-Pin PLCC Le58QL061VC 6 44-Pin TQFP Zarlink Semiconductor Inc CS/PG DCLK/ DIO/S1 36 TSCA 35 DGND 34 PCLK/DCL 33 VCCD DXA/ FS/FSC 30 RST 29 INT CS/PG 32 DCLK/S0 31 DIO/S1 30 TSCA 29 DGND 28 PCLK/DCL 27 VCCD DXA/ FS/FSC 24 RST 23 INT ...
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... Pins of same name on the Le58QL063VC device are internally connected (AGND, pins 10, 11; VCCA, pins 7, 8; VCCD, pins 38, 39; DGND, pins 42, 43 Le58QL063VC 64-Pin LQFP Zarlink Semiconductor Inc CS/PG 47 DCLK/S0 46 DIO/S1 TSCA 45 44 TSCB 43 DGND 42 DGND 41 PCLK/DCL RSVD 40 VCCD 39 38 VCCD 37 ...
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... Additionally, CD1 can be demultiplexed into two separate inputs using the E1 demultiplexing function. The E1 demultiplexing function of the QLSLAC device was designed to interface directly to Zarlink SLIC devices supporting the ground key function. With the proper Zarlink SLIC device and the E1 function of the QLSLAC device enabled, the CD1 bit can be demultiplexed into an Off-Hook/Ring Trip signal and Ground Key signal ...
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... Frame Sync. In GCI mode, the Frame Sync (FSC) pulse kHz signal that identifies the Input beginning of GCI channel system’s GCI frame. The QLSLAC device references individual GCI channels with respect to this input, which must be synchronized to DCL. Description 10 Zarlink Semiconductor Inc. ...
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... MHz, 1.544 MHz, or 2.048 MHz (times clock for use by the digital signal processor. MCLK/E1 Input/Output If the internal clock is derived from the PCM Clock Input (PCLK GCI mode is selected, this pin can be used output to control Zarlink SLIC devices having multiplexed hook switch and ground key detector outputs. NC — ...
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... Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile. OPERATING RANGES Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling ...
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... Digital Input capacitance I C Digital Output capacitance O Power supply rejection ratio (1.02 kHz, 100 mV PSRR path dB) = 400 µ AGND OUT , either RMS 13 Zarlink Semiconductor Inc. Min Typ Max Unit 0.8 V 2.0 –7 +7 µA –120 +180 0.16 0.25 0.34 V 0.4 0.8 V 0.4 0.4 – ...
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... Hz 0 dBm0 300 to 3400 Hz 0 dBm0 SLIC imped. <300 Ω (Le58QL061), <5000 Ω (Le58QL063) 1014 Hz, Average 1014 Hz, Average Zarlink Semiconductor Inc. , then the output offset will be multiplied AISN = DGND and with no load connected to IL Receive Unit 0.5024 0.4987 Vrms ...
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... Figure 1. Transmit Path Attenuation vs. Frequency 1.8 0.125 0 -0.125 2..N) are closely spaced ----- - C f • ----- - C f • – ∑ • --------------------------------------------------------------- - --------- - log – j -------------------------------------------------------------------------------------------------------- - ---- - log Acceptable Region Frequency (Hz) 15 Zarlink Semiconductor Inc. – 10 dBm0. 0.75 0 ...
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... Figure 2. Receive Path Attenuation vs. Frequency 2 1 0.125 Acceptable Region 0 -0.125 Frequency (Hz Zarlink Semiconductor Inc. 0.75 0 ...
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... Hz. Figure 4. A-law Gain Linearity with Tone Input (Both Paths) 1.5 Gain (dB) 0.55 0.25 -0.25 -0.55 -1.5 Figure 3. Group Delay Distortion Acceptable Region 90 0 Frequency (Hz) Acceptable Region 0 -55 -50 -40 17 Zarlink Semiconductor Inc. µ -law) for either Input Level - (dBm0) ...
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... Figure 6. Total Distortion with Tone Input (Both Paths -45 -40 µ -law Gain Linearity with Tone Input (Both Paths) 1.4 Acceptable Region 0 -55 -50 -37 Acceptable Region -30 Input Level (dBm0) 18 Zarlink Semiconductor Inc. Input Level +3 -10 0 (dBm0) A A-Law µ-Law A 35.5dB 35.5dB B 35.5dB 35.5dB C ...
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... A ≤ 0 dBm0 –25 dBm0 < A ≤ 0 dBm0 3.4 4.0 4.6 Frequency (kHz) π 4000 f – ( Attenuation (db – sin ---------------------------- - 1200 19 Zarlink Semiconductor Inc. Level below see Figure - Level –32 dBm0 –46 dBm0 –36 dBm0 ...
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... Figure 9. Analog-to-Analog Overload Compression Fundamental Output Power (dBm0) π f 4000 ( ) – ---------------------------- - Level = – 14 – 14 sin 1200 Figure 8. Spurious Out-of-Band Signals 3.4 4.0 4.6 Frequency (kHz Acceptable 2 Fundamental Input Power (dBm0) 20 Zarlink Semiconductor Inc. dBm0 -28 dBm0 -32 dBm0 Region ...
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... DRS t 36 PCM data input hold time DRH Parameter Min 122 2500 2500 3 50 Parameter Min. 122 Zarlink Semiconductor Inc. Typ Max Unit Note –10 DCY t –20 DCH 8t DCY 1 ns 2500 t –10 DCY t –20 DCH 8t DCY µs Typ Max Unit Note ...
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... If PCLK or MCLK has jitter, care must be taken to ensure that all setup, hold, and pulse width requirements are met. 7. Phase jumps will be present when the master clock frequency is a multiple of 1.544 MHz. Parameter Min 48 48 Parameter Min CHP = 1 , where N is the value stored in the time/clock-slot register. PCY 22 Zarlink Semiconductor Inc. Typ Max Unit Notes Typ Max Unit ...
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... SWITCHING WAVEFORMS Figure 10. Input and Output Waveforms for AC Tests 2.4 V 0.45 V Figure 11. Microprocessor Interface (Input Mode DCLK Data D I/O Valid Outputs CD1 - C7 2.0 V TEST POINTS 0 Data Data Valid Valid Data Valid 23 Zarlink Semiconductor Inc. 2 Data Valid ...
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... V Three-State Data OH D I/O Valid V OL Figure 13. PCM Highway Timing for (Transmit on Negative PCLK Edge PCLK TSCA/ TSCB DXA/DXB DRA/DRB Data Data Valid Valid Time Slot Zero Clock Slot Zero First Bit First Second Bit Bit Zarlink Semiconductor Inc Three-State ...
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... Figure 14. PCM Highway Timing for (Transmit on Positive PCLK Edge PCLK TSCA/ TSCB DXA/DXB DRA/DRB Time Slot Zero Clock Slot Zero First Bit First Second Bit Bit Zarlink Semiconductor Inc ...
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... PCLK FS DXA/DXB, DRA/DRB PCR PCF PCLK 23 t PCH FSS DXA/DXB t DXD 32 DRA/DRB Figure 15. Double PCLK PCM Timing First Bit Detail Below PCY 28 t FSH 35 26 Zarlink Semiconductor Inc. Second Bit t PCL DRS DRH ...
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... The Data Clock (DCL) can be stopped in the high or low state without loss of information. Figure 16. Master Clock Timing Parameter Min F = 2.048 kHz DCL F = 4.096 kHz DCL F = 2.048 kHz DCL F = 4.096 kHz DCL 130 twH + Zarlink Semiconductor Inc. 38 Typ Max Unit Notes 488 244 – 50 DCL 100 150 1 2 ...
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... GCI Waveforms DCL 4.096 MHz FS DD DCL dDF DU t dDC DD Figure 17. 4.096 MHz DCL Operation Bit 7 Detail Below DCL wFH 28 Zarlink Semiconductor Inc. Bit ...
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... DCL 2.048 MHz FS DD DCL dDF DU t dDC Figure 18. 2.048 MHz DCL Operation Bit 7 Bit 6 Detail Below f t DCL wFH Zarlink Semiconductor Inc. Bit ...
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... GCI more than 2 FS) and DCLK does not have ac clock present Power On or Commands have been sent PCM Hardware in PCM state and Hardware Reset Reset generated Power On or GCI Hardware Not allowed Reset 30 Zarlink Semiconductor Inc. Table 3 lists the selection Requirement , 1 ...
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... In this mode, the MCLK/E1 pin is free to be used signal output. In GCI mode, since the master clock is derived only from the DCL clock, this MCLK/E1 pin is always available output. Clock mode options and E1 output functions are shown in Figure 19. 31 Zarlink Semiconductor Inc. ...
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... Real Time Data register, MPI Command 4D/4Fh, GCI Command SOP 13, GCI C/I Channel) using the E1 multiplex mode. This multiplex mode provides the means to accommodate dual detect states when connected to an Zarlink SLIC device, which also supports ground-key detection in addition to loop detect. Zarlink SLIC devices that support ground-key detect use their E1 pin as an input to switch the SLIC device’ ...
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... CDA 4 ATI (MPI Command 70/71h or GCI Command SOP 5) MCDB MCDA MCDB Zarlink Semiconductor Inc. before allowing any change to the CD1 C4 C3 CD2 CD1 0 MUX Debounce Time (set via MPI Command C8/C9h or GCI Command SOP 11) Real Time Data Register (MPI Command 4D/4Fh ...
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... Contains CD1 Pin CD1 Pin State Valid GK State Ignored Ignored Status Hold Last State Tracks Hold Last State Hold Last State DET State 34 Zarlink Semiconductor Inc. Contains Valid LD Status Tracks DET State ...
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... In the GCI mode, this real-time data is also available in the field of the upstream SC octet. Figure 22. MPI Real-Time Data Register DSH0 – DSH3 Debounce Period (0 – Loop Detect Debounce Filter MUX UP/DN Q Six-State RST Up/Down Clock Divider Counter (1 – clock output) b. Ground-Key Filter 35 Zarlink Semiconductor Inc CDA Debounce Counter EN/HOLD * Q CK RST CDB ...
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... VMODE bit. All circuits that contain programmed information retain their data in the Inactive state. Chopper Clock The Le58QL063 device provides a chopper clock output to drive the switching regulator on some Zarlink SLIC devices. The clock frequency is selectable as 256 or 292.57 kHz by the CHP bit (MPI Command 46/47h, GCI Command SOP 6). The duty cycle is given in the Switching Characteristics section ...
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... GX mator mator * Inter- Inter polator polator * Lower Receive Gain (LRG) * programmable blocks Electrical Characteristics, on page 37 Zarlink Semiconductor Inc. Cutoff Transmit Path (CTP) LPF & Com- X TSA HPF pressor * TSA Loopback (TLB) Cutoff Receive Path (CRP) Ex- R LPF TSA Digital pander ...
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... Transmit logic controls the transmission of data onto the GCI bus as determined by the frame synchronization signal (FSC) and the S0 and S1 channel select bits. No signaling or Linear mode options are available when GCI mode is selected. for the value). Gain block analog gain 6.02 dB (unity gain or gain 38 Zarlink Semiconductor Inc. ...
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... SLIC device echo gain into an open circuit, G 440 SLIC device input impedance without the QLSLAC device. • ( • ) ⁄ – – AISN is the SLIC device echo gain into a short circuit, and Zarlink Semiconductor Inc. ) given by: IN • 440 AISN is the SL ...
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... Robbed-bit signaling is only available in the µ-law companding mode of the device. Also, only the 4 ∑ • • 0.0625 GIN AISN AISN i value of AISN = 00000 specifies a gain of 0 (or cutoff), and 2) a value AISN 40 Zarlink Semiconductor Inc. – 16 page 21. µ -law Companded mode must be specified ...
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... GX gain = +6 dB, GR gain = –8.984 dB AX gain = 0 dB, AR gain = 0 dB, input attenuator on (DGIN = 0) R filter: H( filter: H( filter: H( filter: H( AISN = cutoff Figure 24. Robbed-Bit Frame PCLK FS Normal Frame (Not Robbed-Bit) PCLK FS Robbed-Bit Frame page 87. This SLIC device has a transmit gain of 0.5 (GTX) and 41 Zarlink Semiconductor Inc. ...
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... E8/E9h 55h 00h, 0Eh 42 Zarlink Semiconductor Inc. GCI — — COP 2 COP 3 COP 5 COP 8 COP 6 COP 7 COP 4 COP 9 — COP1 SOP 10 SOP 8 SOP 7 — — — ...
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... C8/C9h 46/47h 46/47h 46/47h 4A/4Bh 4A/4Bh 4A/4Bh C8/C9h C8/C9h C8/C9h C8/C9h 6C/6Dh Description MPI 4D/4Fh 54/55h 73h — — 43 Zarlink Semiconductor Inc. GCI SOP 10 SOP 10 — GCI — — — SOP 6 SOP 6 SOP 11 — — — — SOP 9 — SOP 11 SOP 11 SOP 11 — ...
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... C8/C9h CDh E8/E9h Note: *All codes not listed are reserved by Zarlink and should not be used. Description Deactivate (Standby state) Software Reset Hardware Reset No Operation Activate (Operational state) Write/Read Transmit Time Slot and PCM Highway Selection Write/Read Receive Time Slot and PCM Highway Selection Write/Read REC & ...
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... Command This command places the device in the Active mode and sets CSTAT = 1. No valid PCM data is transmitted until after the second FS pulse is received following the execution of the Activate command page 36 of the section Operating the QLSLAC Device Zarlink Semiconductor Inc. page 82 ...
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... Transmit on Highway A (see TAB in Commands 44/45h) Transmit on Highway B (see TAB in Commands 44/45h) Time Slot Number (TTS0 is LSB, TTS6 is MSB RPCM RTS6 RTS5 RTS4 Receive on Highway A Receive on Highway B Time Slot Number (RTS0 is LSB, RTS6 is MSB) 46 Zarlink Semiconductor Inc R/W TTS3 TTS2 TTS1 TTS0 ...
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... MCLK used as master clock multiplexing allowed PCLK used as master clock; E1 multiplexing allowed if enabled in Command C8/C9h. 1.536 MHz 1.544 MHz 2.048 MHz Reserved Two times frequency specified above (2 x 1.536 MHz, Four times frequency specified above (4 x 1.536 MHz, 47 Zarlink Semiconductor Inc ...
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... CDB CDA CDB CDA Debounced data bit 1 on channel 1 Data bit 2 or multiplexed data bit 1 on channel 1 Debounced data bit 1 on channel 2 Data bit 2 or multiplexed data bit 1 on channel 2 48 Zarlink Semiconductor Inc R/W EC4 EC3 EC2 EC1 µ -law is selected ...
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... DGIN AX AR AISN4 Input attenuator on Input attenuator off 0 dB gain 6.02 dB gain 0 dB loss 6.02 dB loss See below (Default value = • • • 16 AISN4 + 8 AISN3 + 4 AISN2 CD1B C5 49 Zarlink Semiconductor Inc R/W AISN3 AISN2 AISN1 AISN0 • AISN1 + AISN0 – R/W C4 ...
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... CD1 is an input CD1 is an output C/L A/µ EGR EGX Compressed coding Linear coding A-law coding µ-law coding Default GR filter enabled Programmed GR filter enabled Default GX filter enabled Programmed GX filter enabled Default X filter enabled 50 Zarlink Semiconductor Inc R/W IOD4 IOD3 IOD2 IOD1 ...
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... Channel number (1 through CTP CRP HPF LRG Transmit path connected Transmit path cut off Receive path connected Receive path cutoff (see note) Transmit Highpass filter enabled Transmit Highpass filter disabled 6 dB loss not inserted 51 Zarlink Semiconductor Inc R/W MCDA MCDB MCDA ...
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... RCN7 RCN6 RCN5 RCN4 C40 m40 C20 m20 m10 m20 – – • { • C20 C30 2 = 1.995 (6 dB)). Zarlink Semiconductor Inc RCN3 RCN2 RCN1 RCN0 R/W C30 m30 C10 m10 m30 m40 – – • ( • C40 ...
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... C2i 2 1 C3i – m26 { • C26 2 53 Zarlink Semiconductor Inc R/W C30 m30 C10 m10 – m30 – m40 ( • C40 R/W C30 m30 C10 m10 C31 m31 C11 m11 C32 ...
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... B = C1i C2i m111 m211 – – • { • = C111 C211 2 coefficients page 52. 54 Zarlink Semiconductor Inc R/W C22 m22 C33 m33 C13 m13 C24 m24 C35 m35 C15 m15 C26 m26 C37 m37 C17 m17 C28 m28 ...
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... C25 m25 – – – – m1i • C1i 2 1 page 52. 55 Zarlink Semiconductor Inc R/W C30 m30 C10 m10 C31 m31 C11 m11 C32 m32 C12 m12 C33 m33 C13 m13 C34 m34 C14 m14 C35 m35 C15 m15 4 5 – ...
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... – m2i – m3i { • [ • C2i C3i 0.9902) page 52. 56 Zarlink Semiconductor Inc R/W C36 m36 C16 m16 C30 m30 C10 m10 C31 m31 C11 m11 C32 m32 C12 m12 C33 m33 C13 m13 C34 m34 C14 m14 C35 ...
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... C2i C3i 2 1 – m26 { • C26 2 page 52. is the actual IIR filter gain value defined by the programmed coefficients, but it also in- 5 gain and normalization, is actually Zarlink Semiconductor Inc R/W C311 m311 C111 m111 54 R/W ...
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... C2i C3i – m26 { • C26 2 page 52. is the actual IIR filter gain value defined by the programmed coefficients Zarlink Semiconductor Inc R/W C35 m35 C15 m15 C16 m16 C37 m37 C17 m17 – 1 • • • ...
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... Double PCLK operation is off. PCLK and PCM data at same rate. Double PCLK enabled. PCLK operates at twice the PCM data rate. Chopper output (CHCLK) turned off Chopper output (CHCLK) turned XDAT6 XDAT5 XDAT4 RSVD RSVD RSVD µ -law transmit data in Companded mode. 59 Zarlink Semiconductor Inc R/W DSH1 DSH0 DPCK ECH ...
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... MHz or 4.096 MHz. The QLSLAC device determines the incoming clock frequency and adjusts internal timing automatically to accommodate single or double clock rates RSVD RSVD RSVD RSVD Filter sampling period Table 8. GCI Channels # 0 & & & & Zarlink Semiconductor Inc R/W GK3 GK2 GK1 GK0 ...
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... Figure 25. Time Slot Control and GCI Interface Voice data for B1 byte Voice data for B2 byte C/I Data Monitor Data FS Time Slot S0 Control S1 Voice data for B1 byte Voice data for B2 byte C/I Data Monitor Data Upstream Multiplexer Downstream Demultiplexer 61 Zarlink Semiconductor Inc. DU DCL DD ...
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... For the 44-pin package device, the downstream SC octet is defined as: <---------------- Downstream SC Octet ------------------> MSB CD2 |<------------------- C/I Field ------------------->| Figure 26. Multiplexed GCI Time Slot Structure 8−11 12−15 16−19 CHN2 CHN3 CHN4 C/I LSB CD1 Zarlink Semiconductor Inc. 20−23 24−27 28−31 CHN5 CHN6 CHN7 ...
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... If the received pattern is the same as the pattern currently in the C/I register, the C/I register is unchanged and the latch is reset. Figure 27. Security Procedure for C/I Downstream Bytes Receive New C/I Code = I ? Store in S Receive New C/I Code = LSB Yes No I: C/I Register Contents S: C/I Secondary Register Contents Yes Load C/I Register with New Code No Yes No 63 Zarlink Semiconductor Inc. ...
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... An inactive (high) MX and MR pair bit for two or more consecutive frames shows an idle state on the monitor channel and the end of message (EOM). LSB CDA CD2 , and 2nd Byte ACK ACK 1st Byte 2nd Byte 125 µs 64 Zarlink Semiconductor Inc. bit in the E1 demultiplexed mode. C 3rd Byte EOM ACK 3rd Byte ...
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... MX ... MX - bit calculated and expected on the DU line RQT ... Request for transmission from internal source Figure 29. Monitor Transmitter Mode Diagram Idle MX=1 ⋅ MR RQT ⋅ MR RQT 1st byte MX=0 ⋅ MR RQT MR nth byte ACK, MX=1 ⋅ MR RQT MR ⋅ MR RQT wait for ACK, MX=0 65 Zarlink Semiconductor Inc. ...
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... State MX Abort ABT MX State • nth Byte Received MR: MR bit transmitted on DU line MX: MX bit received on DD line LL: Last look at monitor byte received ABT: Abort indication from internal source Zarlink Semiconductor Inc. Any MX Wait for • LL • • Wait for 21108A-033 ...
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... Control byte, read Data byte 1 Data Byte n m ≤ ≤ Channel 1 is the destination Channel 2 is the destination Channel 1 is the source Channel 2 is the source D D Description Transceiver Transceiver 1 0 Analog Transceiver 1 1 Future 67 Zarlink Semiconductor Inc. • CONF CONF CONF CONF ...
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... Write/Read AISN & Analog gains 80/81h Write/Read GX Filter Coefficients 82/83h Write/Read GR Filter Coefficients 98/99h Write/Read Z Filter Coefficients (FIR) 86/87h Write/Read B1 Filter Coefficients (FIR) 88/89h Write/Read X Filter Coefficients 8A/8Bh Write/Read R Filter Coefficients 96/97h Write/Read B2 Filter Coefficients (IIR) 9A/9Bh Write/Read Z Filter (IIR) 68 Zarlink Semiconductor Inc Description ...
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... ADDRESS Control byte, TOP read TOP Byte 1 TOP Byte RCN7 RCN6 RCN5 RCN4 GCI Monitor Channel Downstream ADDRESS CR1 • • CRm SOP Read m ≤ Zarlink Semiconductor Inc. 10. Upstream • • n ≤ RCN3 RCN2 RCN1 RCN0 Table 11. Upstream CR1 • • ...
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... SOP 5. Write/Read Configuration Register 1 (CR1), Operating Conditions GCI Command (70/71h) Operating Conditions (Configuration Register 1, CR1) Command I/O Data Configuration register CR1 enables or disables test features and controls feeding states. The reset value of CR1 = 04H CTP CRP HPF LRG ATI 70 Zarlink Semiconductor Inc page 36 R/W ILB FDL TON ...
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... Full Digital Loopback disabled Full Digital Loopback enabled 1 kHz receive tone off 1 kHz receive tone INTM CHP RSVD RSVD TTL-compatible output Open drain output Chopper Clock is 256 kHz (2048/8 kHz) Chopper Clock is 292.57 kHz (2048/7 kHz) 71 Zarlink Semiconductor Inc R/W RSVD RSVD RSVD RSVD ...
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... Z filter default coefficients used Z filter programmed coefficients used B filter default coefficients used B filter programmed coefficients used RSVD CSTAT CFAIL IOD5 Channel is inactive (Standby mode) Channel is active The internal clock is synchronized to frame sync The internal clock is not synchronized to frame sync 72 Zarlink Semiconductor Inc R ...
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... VOUT high impedance when channel is inactive. LPM reduced the power in the QSLAC device, but it is not needed and not used in the QLSLAC device CD1B EE1 E1P DSH3 DSH2 E1 Multiplexing is turned off E1 Multiplexing is turned high-going pulse low-going pulse 73 Zarlink Semiconductor Inc R/W RSVD CD2 CD1 ...
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... Data bit 2 or multiplexed data bit 1 on Channel 1 Debounced data bit 1 on Channel 2 Data bit 2 or multiplexed data bit 1 on Channel 2 Debounced data bit 1 on Channel 3 Data bit 1 on Channel 3 Debounced data bit 1 on Channel 4 Data bit 2 or multiplexed data bit 1 on Channel 4 74 Zarlink Semiconductor Inc ...
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... ADDRESS Command byte, COP write Data1 • • Data m Control byte, COP read Data Data m ≤ ≤ CMD CMD CMD CMD DATA DATA DATA DATA DATA DATA DATA DATA 75 Zarlink Semiconductor Inc R/W MCDB MCDA MCDB MCDA Table 12. 1 • • ...
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... AISN4 + 8 AISN3 + 4 AISN2 C40 m40 C20 m20 m10 m20 – – • ( • ( C10 C20 C30 2 76 Zarlink Semiconductor Inc please refer to the W/R ASIN3 AISN2 AISN1 AISN0 • AISN1 + AISN0 – W/R C30 ...
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... C41 m41 C21 m21 C42 m42 C22 m22 C43 m43 C23 m23 C44 m44 C24 m24 – 1 – 2 – 3 – 4 • • • • Zarlink Semiconductor Inc W/R C30 m30 C10 m10 m30 m40 – ( • C40 R/W C30 m30 ...
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... B Sample rate = 16 kHz – m2i – m3i [ • ( • C2i C3i 2 – m111 – m211 { • [ • C211 C311 2 78 Zarlink Semiconductor Inc. m4i – • C4i R/W C22 m22 C33 m33 C13 m13 C24 m24 C35 m35 C15 m15 ...
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... – m1i – m2i – • ( • ( • C2i C3i page 76. 79 Zarlink Semiconductor Inc W/R C30 m30 C10 m10 C31 m31 C11 m11 C32 m32 C12 m12 C33 m33 C13 m13 C34 m34 C14 m14 C35 m35 C15 m15 – ...
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... FIR – m1i – m2i – • { • [ • 1 C2i 2 1 C3i 0.9902) page 76. 80 Zarlink Semiconductor Inc W/R C36 m36 C16 m16 C30 m30 C10 m10 C31 m31 C11 m11 C32 m32 C12 m12 C33 m33 C13 m13 C34 m34 ...
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... C2i C3i 2 – m16 • { • C16 C26 2 6 page 76. 81 Zarlink Semiconductor Inc W/R C311 m311 C111 m111 R/W C35 m35 C15 m15 C16 m16 C37 m37 C17 m17 – 1 • • ...
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... the maximum and minimum values are ±3, i Equation 5 – – • • • – m3 – m4 • ( • Zarlink Semiconductor Inc defined in the following i bits to the right of the decimal 1 bits to the right of the 3 is also 0, the result is another binary – • • • • Equation 6 Equation 7 ...
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... Receive Tone (TON): When TON = kHz digital mW is injected into the receive path, replacing any receive or downstream signal. , consists of N CSD coefficients, each being made bits and formatted as Cxy mxy coefficient. The most significant binary 1 is represented The i Equation 8 page 44 for complete details on programming the coefficients. 83 Zarlink Semiconductor Inc. ) coefficient. 3 ...
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... Zarlink Semiconductor Inc. µ -law PCM encoding Character Signal pre Quantized Decoder Inversion of Value (at Output Even Bits Decoder Value No. Output) y Bit No 4032 128 See Note 2112 113 See Note 1056 ...
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... Zarlink Semiconductor Inc Character Signal pre Quantized Decoder Inversion of Value (at Output Even Bits Decoder Value No. Output) y Bit No 8031 127 See Note 4191 112 See Note 2 2079 See Note 1023 80 See Note 495 64 See Note 2 ...
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... The output from the WinSLAC program includes the coefficients of the GR, GX and B filters as well as transmission performance plots of two-wire return loss, receive and transmit path frequency responses, and four-wire return loss. The software supports the use of the Zarlink SLIC devices or allows entry of a SPICE netlist describing the behavior of any type of SLIC device circuit. ...
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... Type Value Tol. 0.1 µF 20% 0.1 µF 20% 0.1 µF 20% 0.1 µF 20% 57.6 kΩ 1% 0.15 µF 20% 178 kΩ Ω See Note 50 Ω 87 Zarlink Semiconductor Inc. +3.3 V VCCA VCCD U2 C BPD Le58QL061 DGND PCM/MPI QLSLAC MODE AGND VIN 1 MLCK/E1 MCLK/E1 VOUT PCLK/DCL PCLK 1 ...
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... Lead tweeze shall be within 0.0045 inch on each side as measured from a vertical flat plane. Tweeze is measured per AMD 06-500. 9 Lead pocket may be rectangular (as shown) or oval. If corner If corner lead pockets are connected then 5 mils minimum corner lead spacing is required. 44-Pin PLCC 88 Zarlink Semiconductor Inc. Dwg rev. AN; 8/00 ...
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... The top of package is smaller than the bottom of the package by 0.15mm. 12. This outline conforms to Jedec publication 95 registration MS-026 13. The 160 lead is a compliant depopulation of the 176 lead MS-026 variation BGA. 44-Pin TQFP 89 Zarlink Semiconductor Inc. ...
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... LQFP LQFP 064 Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing. LQFP 064 90 Zarlink Semiconductor Inc. Dwg rev. AS; 8/00 ...
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... Added "Packing" column and Note 2 to Revision • Modified GAISN specifications in Revision • Enhanced format of package drawings in • Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 13, changed C and C from 21, changed t17, t19, and t20 from Ordering Information, on page 1 Electrical Characteristics, on page 13 ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...