LE58QL063HVC Zarlink, LE58QL063HVC Datasheet - Page 74

• Manufacturer Part Number: LE58QL063HVC
• Description: SLIC 4-CH 3.3V 64-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of LE58QL063HVC

• Package: 64LQFP
• Number Of Channels Per Chip: 4
• Polarity Reversal: Yes
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

RSVD
Enable Chopper (Global parameter)
Power Up and Hardware Reset (RST) Value = 20h
Note:
* This command applies to all four channels of the device.
SOP 12. Write/Read Ground Key Filter Sampling Interval
Filter Ground Key
RSVD
Power Up and Hardware Reset (RST) Value = x0h.
SOP 13. Read Real-Time Data Register
Real Time Data
This data is also available in the C/I field of the upstream SC channel.
Command
I/O Data
Command
I/O Data
GCI Command
(E8/E9h)
R/W = 0: Write
R/W = 1: Read
GCI Command
(4D/4Fh)
C = 0: Do not clear interrupt
C = 1: Clear interrupt
This register reads real-time data with or without closing the interrupt.
DSH = 0–15
DSH contains the debouncing time in ms of the CD1 data (usually hook switch) entering the CD1B bit of the
Default = 8 ms
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
ECH = 0*
ECH = 1
GK = 0–15
GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or CD2 entering the
upstream C/I channel described earlier.
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
CDA
CDB
CDA
CDB
CDB
CDA
CDB
CDA
1
1
2
2
3
3
4
4
read SLIC device Input/Output register and the CD1B transmitted on the C/I bit of the upstream SC
channel. The input data on CD1 must remain stable for the debounce time in order for the state of
CD1B to change.
Debounce period in ms
Chopper clock output is turned off.
Chopper clock output is turned on.
Filter sampling period in ms
Debounced data bit 1 on Channel 1
Data bit 2 or multiplexed data bit 1 on Channel 1
Debounced data bit 1 on Channel 2
Data bit 2 or multiplexed data bit 1 on Channel 2
Debounced data bit 1 on Channel 3
Data bit 1 on Channel 3
Debounced data bit 1 on Channel 4
Data bit 2 or multiplexed data bit 1 on Channel 4
RSVD
CDB
D
D
1
0
7
7
4
Zarlink Semiconductor Inc.
RSVD
CDA
D
D
1
1
6
6
4
74
RSVD
CDB
D
D
1
0
5
5
3
RSVD
CDA
D
D
0
0
4
4
3
CDB
GK3
D
D
1
1
3
3
2
CDA
GK2
D
D
0
1
2
2
2
CDB
GK1
D
D
C
0
1
1
1
CDA
GK0
R/W
D
D
1
0
0
1