LE58QL063HVC Zarlink, LE58QL063HVC Datasheet - Page 49

• Manufacturer Part Number: LE58QL063HVC
• Description: SLIC 4-CH 3.3V 64-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of LE58QL063HVC

• Package: 64LQFP
• Number Of Channels Per Chip: 4
• Polarity Reversal: Yes
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

This command does not depend on the state of the Channel Enable Register.
50/51h Write/Read AISN and Analog Gains
Disable Input Attenuator (GIN)
Transmit Analog Gain
Receive Analog Loss
AISN coefficient
* Power Up and Hardware Reset (RST) Value = 00h.
52/53h Write/Read SLIC Device Input/Output Register
Pins CD1, CD2, and C3 through C7 are set to 1 or 0. The data appears latched on the CD1, CD2, and C3 through C5 SLIC
Command
I/O Data
Command
I/O Data
MPI Command
R/W = 0: Write
R/W = 1: Read
MPI Command
R/W = 0: Write
R/W = 1: Read
h
AISN
CDA
CDB
CDA
CDB
DGIN = 0*
DGIN = 1
AX = 0*
AX = 1
AR = 0*
AR = 1
AISN = 0* – 31
The Impedance Scaling Network (AISN) gain can be varied from −0.9375 • GIN to +0.9375 • GIN in
multiples of 0.0625 • GIN.
The gain coefficient is decoded using the following equation:
where h
a value of AISN = 0000* indicates a gain of 0 (cutoff).
device I/O pins, provided they were set in the Output mode (see Command 54/55h). The data sent to any of
the pins set to the Input mode is latched, but does not appear at the pins. The CD1B bit is only valid if the
E1 Multiplex mode is enabled (EE1 = 1). C7 and C6 are outputs only and are not available on all package
types.
* Power Up and Hardware Reset (RST) Value = 00h
=
3
3
4
4
0.0625 GIN
AISN
is the gain of the AISN. A value of AISN = 10000 turns on the Full Digital Loopback mode and
•
Debounced data bit 1 on channel 3
Data bit 2 or multiplexed data bit 1 on channel 3
Debounced data bit 1 on channel 4
Data bit 2 or multiplexed data bit 1 on channel 4
Input attenuator on
Input attenuator off
0 dB gain
6.02 dB gain
0 dB loss
6.02 dB loss
See below (Default value = 0)
[
(
16 AISN4
DGIN
C7
D
•
D
0
0
7
7
Zarlink Semiconductor Inc.
+
AX
C6
D
D
1
1
8 AISN3
6
6
•
49
CD1B
AR
D
D
0
0
5
5
+
4 AISN2
•
AISN4
C5
D
D
1
1
4
4
+
AISN3
2 AISN1
C4
D
D
0
0
3
3
•
AISN2
D
D
C3
0
0
2
2
+
AISN0
AISN1
CD2
D
D
0
1
1
1
) 16
–
AISN0
]
CD1
R/W
R/W
D
D
0
0