MT45W256KW16BEGB-708 WT Micron Technology Inc, MT45W256KW16BEGB-708 WT Datasheet - Page 6

• Manufacturer Part Number: MT45W256KW16BEGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W256KW16BEGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Ball Descriptions
Table 1:
PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5
8mb_4mb_burst_cr1_0_p22z__2.fm - Rev. B 4/ 08 EN
G4, G3, H5, H4,
H3, H2, D4, C4,
E3, G2, H1, H6,
C3, B4, B3, A5,
D2, C2, C1, B1,
D3, E4, F4, F3,
G1, F1, F2, E2,
G6, F6, F5, E5,
D5, C6, C5, B6
Assignment
J4, J5, J6
VFBGA
A4, A3
A6
A2
G5
A1
D6
D1
H1
B5
B2
E1
E6
J2
J3
J1
VFBGA Ball Descriptions
DQ[15:0]
Symbol
A[17:0]
ADV#
WAIT
V
V
WE#
DNU
OE#
UB#
CLK
CRE
CE#
LB#
V
V
NC
CC
SS
CC
SS
Note:
Q
Q
Output
Output
Supply
Supply
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
The CLK and ADV# inputs can be tied to V
nous or page mode. WAIT will be asserted, but should be ignored during asynchronous
and page mode operations.
–
–
4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory
Description
Address inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address lines
are also used to define the value to be loaded into the BCR or the RCR.
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the address
is latched on the first rising CLK edge when ADV# is active. CLK is static LOW or
HIGH during asynchronous access READ and WRITE operations and during PAGE
READ ACCESS operations.
Address valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during asynchronous READ
and WRITE operations. ADV# can be held LOW during asynchronous READ and
WRITE operations.
Configuration register enable: When CRE is HIGH, WRITE operations load the
RCR or BCR.
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby or DPD mode.
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write enable: Determines whether a given cycle is a WRITE cycle. If WE# is LOW,
the cycle is a WRITE either to a configuration register or to the memory array.
Lower byte enable: DQ[7:0].
Upper byte enable: DQ[15:8].
Data inputs/outputs.
Wait: Provides data-valid feedback during burst READ and WRITE operations. The
signal is gated by CE#. WAIT is used to arbitrate collisions between REFRESH and
READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary.
WAIT is also used to mask the delay associated with opening a new internal page.
WAIT is asserted and should be ignored during asynchronous and page mode
operations. WAIT is High-Z when CE# is HIGH.
Device power supply (1.7–1.95V): Power supply for device core operation.
I/O power supply (1.7–3.6V): Power supply for input/output buffers.
V
V
Not internally connected.
Do not use: DNUs must be left unconnected or tied to ground.
SS
SS
Q must be connected to ground.
must be connected to ground.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SS
if the device is always operating in asynchro-
©2008 Micron Technology, Inc. All rights reserved.
Ball Descriptions