MT45W256KW16BEGB-708 WT Micron Technology Inc, MT45W256KW16BEGB-708 WT Datasheet - Page 10

• Manufacturer Part Number: MT45W256KW16BEGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W256KW16BEGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Functional Description
Power-Up Initialization
Figure 4:
Bus Operating Modes
Asynchronous Mode
PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5
8mb_4mb_burst_cr1_0_p22z__2.fm - Rev. B 4/ 08 EN
Power-Up Initialization Timing
In general, MT45W256KW16BEGB devices are high-density alternatives to SRAM and
PSRAM products, popular in low-power, portable applications.
The MT45W256KW16BEGB contains a 4,194,304-bit DRAM core organized as 262,144
addresses by 16 bits. This device implements the same high-speed bus interface found
on burst mode Flash products.
The CellularRAM bus interface supports both asynchronous and burst mode transfers.
Page mode accesses are also included as a bandwidth-enhancing extension to the asyn-
chronous READ protocol.
CellularRAM products include an on-chip voltage sensor used to launch the power-up
initialization process. Initialization will configure the BCR and the RCR with their default
settings (see Figure 19 on page 24 and Figure 24 on page 28). V
applied simultaneously. When V
device will require 150µs to complete its self-initialization process. During the initializa-
tion period, CE# should remain HIGH. When initialization is complete, the device is
ready for normal operation.
VccQ
The MT45W256KW16BEGB CellularRAM products incorporate a burst mode interface
found on Flash products targeting low-power, wireless applications. This bus interface
supports asynchronous, page mode, and burst mode READ and WRITE transfers. The
specific interface supported is defined by the value loaded into the BCR. Page mode is
controlled by the refresh configuration register (RCR[7]).
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry-standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations
(Figure 5 on page 11) are initiated by bringing CE#, OE#, and LB#/UB# LOW while
keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access
time has elapsed. WRITE operations (Figure 6 on page 11) occur when CE#, WE#, and
LB#/UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a
“Don’t Care,” and WE# will override OE#. The data to be written is latched on the rising
edge of CE#, WE#, or LB#/UB#, whichever occurs first. Asynchronous operations (page
mode disabled) either can use the ADV input to latch the address, or can drive ADV LOW
during the entire READ/WRITE operation.
During asynchronous operation, the CLK input must be held static LOW or HIGH. WAIT
will be driven while the device is enabled, and its state should be ignored. WE# LOW
time must be limited to
Vcc
Vcc = 1.7V
4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory
t
CEM.
Device initialization
10
t PU > 150µs
CC
and V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CC
Q reach a stable level at or above 1.7V, the
Device ready for
normal operation
Functional Description
CC
©2008 Micron Technology, Inc. All rights reserved.
and V
CC
Q must be