MT45W256KW16BEGB-708 WT Micron Technology Inc, MT45W256KW16BEGB-708 WT Datasheet - Page 15

• Manufacturer Part Number: MT45W256KW16BEGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W256KW16BEGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

WAIT Operation
Figure 10:
LB#/UB# Operation
PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5
8mb_4mb_burst_cr1_0_p22z__2.fm - Rev. B 4/ 08 EN
Wired-OR WAIT Configuration
The WAIT output on a CellularRAM device is typically connected to a shared, system-
level WAIT signal (see Figure 10). The shared WAIT signal is used by the processor to
coordinate transactions with multiple memories on the synchronous bus.
After a READ or WRITE operation has been initiated, WAIT goes active to indicate that
the CellularRAM device requires additional time before data can be transferred. For
READ operations, WAIT will remain active until valid data is output from the device. For
WRITE operations, WAIT will indicate to the memory controller when data will be
accepted into the CellularRAM device. When WAIT transitions to an inactive state, the
data burst will progress on successive clock edges.
During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE#
HIGH during this initial latency may cause data corruption.
The WAIT output also performs an arbitration role when a READ or WRITE operation is
launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted
for additional clock cycles until the refresh has completed (see Figure 11 on page 16 and
Figure 12 on page 16). When the refresh operation has completed, the READ or WRITE
operation will continue normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary.
The WAIT assertion allows time for the new row to be accessed and permits any pending
REFRESH operations to be performed.
The LB# enable and UB# enable signals support byte-wide data transfers. During READ
operations, the enabled byte(s) are driven onto the DQ. The DQ associated with a
disabled byte are put into a High-Z state during a READ operation. During WRITE opera-
tions, any disabled bytes will not be transferred to the RAM array, and the internal value
will remain unchanged. During an asynchronous WRITE cycle, the data to be written is
latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will
disable the data bus from receiving or transmitting data. Although the device will seem
to be deselected, it remains in an active mode as long as CE# remains LOW.
Processor
READY
4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory
WAIT
device
Other
CellularRAM
WAIT
15
WAIT
device
Other
Micron Technology, Inc., reserves the right to change products or specifications without notice.
External
pull-up/
pull-down
resistor
Bus Operating Modes
©2008 Micron Technology, Inc. All rights reserved.