MT45W256KW16BEGB-708 WT Micron Technology Inc, MT45W256KW16BEGB-708 WT Datasheet - Page 5

• Manufacturer Part Number: MT45W256KW16BEGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W256KW16BEGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

General Description
Functional Block Diagrams
Figure 2:
PDF: 09005aef8329f3e3 / Source: 09005aef82e419a5
8mb_4mb_burst_cr1_0_p22z__2.fm - Rev. B 4/ 08 EN
ADV#
WAIT
WE#
OE#
UB#
CLK
CRE
CE#
LB#
Functional Block Diagram (256K x 16)
A[17:0]
Note:
Control
logic
Micron
power, portable applications. The MT45W256KW16BEGB is a 4Mb DRAM core
device organized as 256K x 16 bits. This device includes an industry-standard burst
mode Flash interface that dramatically increases read/write bandwidth compared with
other low-power SRAM or pseudo-SRAM (PSRAM) offerings.
For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans-
parent self refresh mechanism. The hidden refresh requires no additional support from
the system memory controller and has no significant impact on device read/write
performance.
Two user-accessible control registers define device operation. The bus configuration
register (BCR) defines how the CellularRAM device interacts with the system memory
bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how refresh is performed on the DRAM
array. These registers are automatically loaded with default settings during power-up
and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh.
This CellularRAM product includes two system-accessible mechanisms to minimize
standby current. Partial-array refresh (PAR) limits refresh to only that part of the DRAM
array that contains essential data. Deep power-down (DPD) halts the REFRESH opera-
tion altogether and is used when no vital information is stored in the device. These two
refresh mechanisms are accessed through the RCR.
Functional block diagrams illustrate simplified device operation. See the ball description
table and timing diagrams for detailed information.
®
CellularRAM
4Mb: 256K x 16 Async/Page/Burst CellularRAM 1.0 Memory
Refresh configuration
Bus configuration
Address decode
register (RCR)
register (BCR)
logic
®
is a high-speed, CMOS PSRAM memory developed for low-
5
256K x 16
memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DRAM
array
buffers
output
Input/
MUX
and
General Description
©2008 Micron Technology, Inc. All rights reserved.
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